Transcript EDA\41_1_variation-

Variation
Sources of Variation
1. Process (manufacturing) (physical) variations:
 Uncertainty in the parameters of fabricated devices and
interconnects
− From die to die
− Within a particular die
2. Environmental (operating context) (temporal) (dynamic) variations:
 Uncertainty in the operating environment of a particular
device during its lifetime
− Temperature
− Supply voltage
− Lifetime wear-out
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Variation Classification
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Supply Voltage Variation
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Temperature Variation
• Temperature Variation:
 Both the device and interconnect performance have
temperature dependence,
− Higher temperature  performance degradation.
Within die temperature variation
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Process Variation
• Process variation: Sample space:
 Set of manufactured dies
 Results in yield loss
− Y = # working die / # manuf. Die
 A small portion of sample space is allowed to fail
timing constraints
− CPU/GPU design: Speed/core binning: for
different applications
−  Lessens the requirement that all or very high
percentage of die meets the fastest timing constraint
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Process Variation
[Cadence]
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Environmental Variation
• Environmental Variation: Sample space:
 Operational life of a chip
 A pessimistic analysis is required
− Should ensure correct operation throughout lifetime
 Design that operates faster than necessary for much of
its operational life
−  loss in efficiency
 One approach:
− Runtime adaptivity of the design
• Environmental Variation: Treated by worst case analysis
• Process variation: Treated statistically
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Process Variation: Sources
•
PV Sources:
 Var. in physical parameters (due to imperfect manufacturing):
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−
−
−
−
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Gate length or critical dimension (CD)
Gate oxide thickness
Channel doping concentration
Interconnect thickness
Interconnect width
…
− Dominant factors: CD and channel doping
  Var. in electrical parameters of components
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−
−
Vth
Drive strength of transistors
Resistance of wires
Capacitance of wires
….
  Var. in circuit characteristics:
− Delay
− Power
− Noise
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Process Variation Sources
x 10-
Leff
2.3
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2.2
2.1
2.0
1.9
1.8
60
100
Wafer X
40
50
20
0
Wafer Y
[IBM, Intel and TSMC]
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Process Variation
• A physical parameter variation may affect more than one
electrical parameter:
 Wire width 
− Wire capacitance
− Wire resistance
− Coupling noise
 Gate oxide thickness 
− Drive current
− Vth
− Cg
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Correlation
 Must consider correlation between electrical parameters
 If ignore correlation (Cw, Rw),
− In theory, both may be at worst–case values
− Impossible in practice
• Correlation among physical parameters themselves
 An equipment variation (e.g. lens deviation) may impact
multiple physical parameter values (all metal layers and
poly)
− Hard to model due to large number of equipment-related
parameters
 Most algorithms take physical parameters to be basic
random variables
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Classification
•
Types of physical-parameter variations:
1. Systematic (deterministic):
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Show predictable variational trends across a chip
Caused by known physical phenomena during manufacturing
Can be predicted upfront by analyzing the designed layout
Can be avoided in final stages
− E.g. Metal fill, optical proximity effects
− But at early stages, common to be treated statistically
- E.g.,regions with uniform
metal densities have more
uniform ILD thicknesses
- Most of the time, not
available to designers/CAD
developers
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Classification
•
Types of physical-parameter variations:
2. Non-systematic (random):
•
− Truly uncertain component of physical-parameter variations
− Resulted from processes that are statistically independent of
the design implementation
− Only the statistical characteristics are known at design time,
−  Must be modeled using RVs
Common practice:
 In earlier stages, both systematic and nonsystematic
variations are modeled statistically
 As we move through the design process and more detailed
information is obtained, the systematic components can be
modeled deterministically (if sufficient analysis capabilities
are available)
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Scaling Effect
 A 22nm MOSFET expected in
mass production
 50 Si atoms along the channel
  Large parameter
fluctuations
 A 4nm MOSFET predicted in
mass production in 2020,
 < 10 Si atoms are expected
along the channel (IBM
roadmap)
  MOS transistors are rapidly
becoming truly atomistic
devices
  Random variations are
becoming dominant.
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Classification
• Classification of variation:
 Die-to-die (inter-die) (global):
− Affects all devices on the same die in the same way
 Within-die: WID (intra-die) (local) (on-chip: OCV):
− Affects each device on the same die differently
− E.g. some devices have larger/smaller CDs than nominal
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D2D Variation
[Menezes07]
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Classification
•
Types of within-die variation:
1. Spatially-correlated:
− Many of the underlying processes that give rise to within-die variation
change gradually from one location to the next.
−  Affect closely spaced devices in a similar manner
−  Make them more likely to have similar characteristics than those
placed far apart
2. Independent:
− Statistically independent from all other devices
− Scaling  Contribution of independent within-die variation is
increasing
−With SC:
− Leff,
− Temperature
− Supply voltage
−No SC:
− tox,
− Dopant concentration
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Inter-die vs. Intra-die Variations
Leff
Inter-die
global
Correlation
Intra-die
spatial
Correlation
• Figures are courtesy of IBM, Intel and TSMC 20
References
• [Blaauw08] Blaauw, Chopra, Srivastava, Scheffer, “Statistical
Timing Analysis: From Basic Principles to State of the Art,” IEEE
Transactions on CAD, Vol. 27, No. 4, April 2008.
• [Forzan09] Forzan, Pandini, “Statistical static timing analysis: A
survey,” Integration, The VLSI Journal, 42, 2009.
• [Menezes07] Menezes, “The Good, the Bad, and the Statistical,”
Invited talk, ISPD 2007.
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