Transcript General
Adaptive On-Chip Test Strategies for Complex Systems V. Stopjaková Department of Microelectronics, STU Bratislava, Slovakia 1 Electronics Industry Trends Achieved successful penetration in different domains Emergence of technology • Greater complexity • Increased performance • Higher density • Lower power dissipation 2 Market-Driven Products Meet user Quality requirements Created an unprecedented Dependency satisfying users to buy products market-driven products Maintain competitive by providing: Greater Product Functionality Lower Cost Reduced Interval (time to market) Higher Reliability 3 High Complexity: Mixed Systems A single chip: Logic, Analog, DRAM blocks Embed advanced blocks: FPGA, Flash, RF/Microwave Others DRAM LOGIC FLASH Analog SRAM FPGA RF MEMS Optical elements Logic 4 High Complexity: Mixed Systems How to test the mixed chip? With external test only - need multiple ATE for a single chip: Logic ATE, Memory ATE, Analog ATE (Double/Triple Insertion) Need special ATE with combined capabilities 5 High Complexity: External Test External Test Data Volume can be extremely high (function of chip complexity) External Test Super ATE Requires deep tester memory for scan I/O pins Pattern Generation Precision Timing Diagnostics Power Management Test Control Slow test with long scan chains Very high pin count Deep memory Slow serial SCAN Memory Logic MixedSignal I/Os & Interconnects Source: LogicVision 6 High Complexity: On-chip Test Solution: Dedicated Built-In Test for embedded blocks Memory On-chip Test External Test Standard Digital Tester Tasks repartitioned into embedded test and Limited Speed/ external test functions Accuracy Logic Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test MixedSignal I/Os & Interconnects Chip, Board or System Source: LogicVision 7 Technology motivation many CMOS defects escaping logic testing physical imperfections causing delay faults unmodeled faults (weak-1, weak-0) Quality & Reliability of IC affected ! Conventional test methods not effective New on-chip test methods have to be applied 8 Supply Current Testing VDD defect I DD IDD IDDT PMOS IDDQ in out NMOS faulty fault-free PASS/FAIL reference t Figure 1 Principle of the supply current testing 9 IDDQ/T testing - realization Off-chip measurement by external equipment On-chip monitoring using Built-In Current (BIC) monitors Off-chip monitors: + no additional chip area needed - slow measurement (decoupling capacitor) - small current masked by noise BIC Monitors: + + - sensitive, very fast and accurate applicable in on-chip methods chip area overhead CUT perturbation 10 IDDQ testing crucial issues Pass/Fail limit setting represents fault-free value of IDDQ current depends on number of factors: technology, type of circuits,... if too high - defective circuits pass if too low - undesired yield decrease (false fault detections) Test vectors Measurement Hardware 11 On-chip IDDQ Monitoring Principle VDD DUT GND’ IDD - Sensing element Vref + Pass/Fail BICM GND Figure 2 On-chip supply current testing 12 Main requirements for on-chip current monitors ability to sense high currents testing of low-voltage circuits a minimal number of extra pins design simplicity applicable for recent VLSI circuits Monitor development focused on: effect on performance of the CUT area overhead testing speed accuracy and sensitivity 13 Example of a quiescent on-chip monitor based on CCII+ current conveyor IDD current measurement current comparison IDDQ sampling VDD BIC Monitor Test CCII+ CC D Pass/Fail CLK iDD VDD’ iref CUT Figure 3 Current conveyor based quiescent BIC monitor 14 BIC monitor layout size of 1 bypass switch is 650m x 210m (80%) total area of 0.22 mm2 Figure 4 The core of the monitor layout 15 Evaluation results resolution of 10nA Pass/Fail limit of 50nA (sensitivity) 1 MHz testing speed VDD degradation max.100mV area overhead of 0.22 mm2 ability to handle large CMOS IC 16 Useful for Differential Analog Test DynamicIDD Monitor IDD VDD References Win Comp IDD SENSOR Pass I (Pass/Fail) SENSO DD R SENSOR LEFT SIGNAL CHANNEL RIGHT SIGNAL CHANNEL ANALOG TEST PATTERN ANALOG OUTPUT Fully Differential Analog Block VSS Figure 5 Experimental BIC monitor usage in a new ABIST approach 17 Current mirror IDD principle R MET VDD ’ I DD I MP1 MP1 MP2 VDD I MP2 I MIR I MIR CUT MN1 MN2 I I offset 1 DD I MP1 PB NB Figure 6 Current mirror principle of IDD monitoring 18 Example of a transient on-chip monitor VDD Vref BIC monitor VDD’ CUT I DD Current Mirror D Vmon A I MIR C MS Voffset Test Figure 7 Transient BIC monitor 19 Experimental digital chip both BIC monitors integrated in BIC-MU BIC-MU implemented into a digital circuit a digital multiplier used as a CUT fabricated in 0.7m CMOS multiplier size 850m 850m area of BIC-MU is 0.24mm2 around 24% of the total chip area 20 Figure 8 Layout of the experimental chip 21 Versatility Problem of IDD Testing IDD testing proven very successful for digital circuits Dedicated fault class only Use in submicron technologies limited IDD testing for analog IC not straightforward Large variety of analog IC Specifications and behavior unique Difficult to generalize analog tests Validation up to now done using functional criteria Current consumption analysis using Neural Networks 22 Artificial Neural Networks Approach Current signature analysis for presence of abnormal (faulty) behavior Massively parallel and distributed structures capable of adaptation No explicit Pass/Fail limit formulation required Excellent versatility Accuracy and sensitivity Reduced number of TP (time to test) 23 IDD analysis using ANN IDD time or freq 1, 0 0, 1 (BAD) (GOOD) Figure 9 ANN-based analysis of IDD 24 Mathematical model x1 bk wk1 xP w kP uk (uk) yk P yk wkj x j bk j 1 Figure 10 Mathematical model of an artificial neuron 25 Activation function Figure 11 Activation function with top and bottom decision levels 26 ANN Classification of tested ICs ANN with two outputs: n1, n2 Classification within top/bottom decision levels n1 TDL & n2 BDL PASS n1 BDL & n2 TDL FAIL Otherwise Non Classified 27 Analog DUT Example Two-stage CMOS operational amplifier A pulse used as input stimuli Good patterns: technology parameters and temperature variations Faulty behavior: basic defects injected (GOS, DOP, SOP, DSS, GSS, GDS) 28 Effect of the GOS Fault Figure 12 Effect of the GOS faults on IDD signal in time and frequency domain 29 Effect of the DSS Fault Figure 13 Effect of the DSS fault on IDD signal in different domains 30 ANN setup 660 tested power supply current waveforms 200 faulty patterns 460 fault-free patterns 32 input nodes various training set: 200, 100, 76, 50 and 26 various number of hidden units: 2, 6, 10, 14, 18, 22 top decision level: 0.9 bottom decision level: 0.1 10 independent measurements 31 PCC[%] Classification results 100 95 90 85 80 75 70 65 60 2 HUs 10 HUs 22 HUs 26 50 76 100 200 Size of Training Set Figure 14 Percent Correct Classification (PCC) for time domain 32 Classification results(2) 100 PCC[%] 95 90 2 HUs 10 Hus 22 HUs 85 80 75 26 50 76 100 200 Size of Training Set Figure 15 Percent Correct Classification for frequency domain 33 Conclusions To ensure quality of SoC Technologies: On-chip Test is added into the designs of embedded cores New adaptive on-chip approaches needed for different test functions On-chip current monitoring effective but not versatile and limited to CMOS digital circuit ANN classification of defective IC ability of testing mixed-signal circuits ability of sensing negligible differences possibility to analyse other circuit’s parameters 34 Thank YOU for your attention! 35