Transcript Presentation Guide

Design & Test
Challenges & Solutions
in Nanometer Era
by
Yervant Zorian
Vice President & Chief Scientist
Virage Logic Corporation
NAS
Agenda
• Market Requirements
• Technology Trends & Challenges
• Design & Test Solutions
• Continuous Technology Innovation
• Conclusions
NAS
1944 - ENIAC – programming and testing
Size- 1 x 2.1 x 33 meters, 140 square meter, contains
19.000 vacuum tubes, 1500 relays, and uses 180 kWh,
its volume was 100 m3 and weighed appr. 30.000 kilo
1947- BINAC
1952
UNIVAC
NAS
Integrated Applications
Drives Cost Reduction/Speeds Market Adoption
Smaller geometries allow us to have more features in smaller footprints.
MSM5500 1xEV-DO Commercial Device (2003)
180nm
Base Band
Power Mgmt.
NAS
Memory
MSM6100 1X Commercial Device (2005)
130nm
Base Band with integrated
co-processor
Power Mgmt.
Memory
Integrated Applications
Drives Cost Reduction/Speeds Market Adoption
Smaller geometries and integration allow us to have more features in smaller footprints.
… Moving to single chip phone!
QSC6030 1x CDMA200 Commercial Device (2006)
QSC6030 Digital Modem &
µProc, BBA, RF & PMIC
Memory
RF
NAS
How to produce this level of integration?
•
The next generation multimedia terminal supports :
– high-bandwidth wireless communication ( ~7mbs) ;
– Multiple modems (Blue tooth, HSUPA, 1x, GSM, WiFi etc),
– Bi-directional motion video;
– High-quality audio(MPEG) ,
CDMA
– Graphics
– Low power
GSM/GPRS
– Integration of RF/ Memory /Analog
– Speech, and pen-based input
DSP
– Full text and graphics input
DSP
– HD TV on Demand
Memory
– Solar charger
– Heads up display / solar insensitive display
– 100% input mapping accuracy
– Full function word processor / spreadsheets, and editing
NAS
MicroProcessor
GPS
3D Graphics
Video
Audio
Imaging
Technology Trends
• Increased number of cores
• Megabits of embedded RAM
• Increasing timing domains and higer frequencies
• More and more power domains and (low) power modes
• Zero PPM quality
• Exploding data volumes
• New process material and more layers
• Intra / Inter die variations
• Gigabit I/O
NAS
Technology Production
• Growth in technology user community continues
• Most complex technologies for children
• Technology users versus producers
• Research -> Development -> Manufacturing
• Producers were Vertically Integrated Systems
companies
– AT&T, DEC, IBM, Philips, Siemens, Hitachi
NAS
1. Problem: Production Cost Challenges
• Capital expenditure for new fabs is increasing at exponential pace
 Process technology development costs are also rising rapidly

Design complexity and cost increase rapidly in advanced node SOCs
ROI Risk
Process Development Cost
New Fabs CapEx
5.0↑
($B)
($B)
50K
wpm
Process
Ramp-Up
Cost
0.7∼1.0
0.4
20K
wpm
6 inch
* WPM : Wafer per Month
NAS
12 inch
Process
Development
Cost
0.4
18 inch
[Source: Samsung]
Required Revenue
> 10x of Design Cost
Software
18.0
20K
wpm
8 inch
($M)
0.8
0.6
30K
wpm
46.2
1.6
1.1
2.5 ∼ 2.9
Design Cost
130
90
65
45
32
D/R
(nm)
[Source: IBS, 2006]
Validation
Physical
9.2
Verification
Architecture
130
90
65
[Source: IBS 2006]
Semiconductor Industry Challenges
Driving Need for Partnerships
• Technology Challenges
– Rising NRE and R&D costs
– Shrinking end-user/product prices
• Market Challenges
– Time-To-Market
– Time-To-Volume
– Competitiveness
NRE & R&D
Costs
NRE & R&D Costs
• Business Challenges
SoCs
End User/Product Prices
– Rapidly shrinking life cycles
– Increasing technology complexity
180nm
130nm
90nm
65nm
Process Technology Node
© 2009 Virage Logic Corporation – COMPANY CONFIDENTIAL
NAS
45nm
1. Disaggregation in Technology Production
Decreasing Overlap Between Principal Disciplines
• Increasing Specialization
Disappearing common language
– Technology complexity
– Increasing gaps between disciplines
• Decreasing ability to communicate in a
common language
Process
EDA
Design
Design Re-spins
Specialization
Depth
• Designers driven to higher levels of
abstraction – distant from process and
test
• Process engineers driven to material,
optics, plasma sciences
‘was’ in the past
‘is’ in the future
Source : Tality
• Increasing Business Segregation
• IDM or Fabless
• IP house or chip house
• ATE, systems, validation or verification
– Solving the test equation is only getting harder.
Complex Multi-Party Relationships
Each Party has its Motivations and Interests
Library
Vendor
Design Kit.
Si
Foundry
ENG
Si
Foundry
Manuf...
Manuf...
IP
Vendor
IP &
Views
Libraries &
Views
Design
Kit
GDS-II
NAS
FE CAD
Vendor
Physical
Tools
Front End
Tools
IC’s
Systems
IC
Design
DESIGN
Wafers
Rules & Models
System level optimization needed
BE CAD
Vendor
Qual
House
HOUSE
Parts
Test
IC
System
Design
DeBug
Protos
Si Wafers
Assembly
Contractor
Test
Contractor
Source : Tality
FA/ DeBug
FIB/etc..
Standardized Solutions
 Pre-Integrated test
and diagnosis IP into
physical IP
 External access - use
of standard interface,
such as \IEEE 1500,
IEEE 1149.1
16
NAS
12
Disaggregated Flow
IP Design
Characterization
SoC Design
Production
Ramp Up
Volume
Fabrication
Test
Assembly
Packaging
In-Field
NAS
Failure
Analysis
Disaggregated Industry
• Creation new companies vs existing companies
– Spin-off culture vs start-ups culture creation
• Rise of Silicon Valley feeding start-ups
–
–
–
–
Stanford University and Hewlett Packard
Concentration of Venture Capital Firms
Enabling environment – Legal, banking, accounting
International contributors (Asian CEOs)
• New companies originated from
– University labs – HP, Google, Yahoo, Oracle, eBAY
– Large industrial corporations – Intel, Nvidia, Cisco,
SUN, LSI Logic, etc.
NAS
2. Trend: Miniaturization Continues
50 nm
30
nm
SiGe S/D
Strained
Silicon
20
nm
35
nm
10
nm
5 nm
SiGe S/D
Strained
Silicon
Metal Gate
High-k
Si Substrate
Nanowire
Tri-Gate
5 nm
S
G
NAS
Alternate
Logic Devices
D
S
III-V
Carbon
Nanotube FET
Source: Intel
Moore’s Law Enabling Significant
Product Opportunities at Same Cost
Better system level power/performance by integrating more functionality
on a single die enabled by the increased availability of transistors
NAS
Moore‘s Law on Wide Range of Products
Highly parallel designs
Multicore designs
IBM Cell
AMD Quadcore
Intel Quadcore
SOC
uP, DSP, GPS, modems, memory
Qualcomm 7600
NAS
nVidia Quad SLI
More Mbytes/ sec =
measure of goodness
More and more timing domains
Megabits of embedded RAM
More and more power domains and (low)power modes
Zero PPM quality
Exploding data volumes
Intra/ Inter die variations
DC to Gigabit I/O
Xilinx Virtex 5
2. Problem: Defectivity
 Miniaturization result in

Finer and denser semiconductor fabrication

Increased susceptiblity

Increased defectivity

Lower manufacturing yield and reliability
 Observed as

Defect density

Realistic Faults

Timing problems

Transient or Soft Errors
NAS
Silicon Quality
• Enhanced Test algorithms with the knowledge of accurate
background patterns provide 100% fault coverage for
comprehensive fault types
– New faults types appear at advanced process technologies
• Resistive faults
• Performance faults
• Bridging faults
• Parametric variation
– Comprehensive modeling of memory topology required to
generate dedicated background patterns for fault detection
– Generic algorithms are not as granular resulting in test
escapes
Lack of knowledge of complete scrambling information
can lead to up to 30% test escapes
© 2009 Virage Logic Corporation
NAS
Silicon Debug Cycle
• Need to gather failure data using diagnosis IP and
analyze obtained data by off-chip fault localization
methodologies, tools and equipment
• Leverage same infrastructure IP for test, silicon
debug and diagnosis
• Integrated Silicon Debug Solution comprised of – Analysis and generation of embedded test &
diagnosis IP
– Integration of embedded test & diagnosis IP
– Creation of yield acceleration data base
– Failure data from diagnosis IP analyzed off-chip
for fault localization
NAS
20
Infrastructure IP for Test and Diagnosis
 Hierarchical network of I-IP
blocks
STAR Fuse Box
STAR Processor n
STAR
SRAM
6IW 1
STAR Processor
1
J
T
A
G
T
A
P
NAS
1
STAR 6IW
Processor
2IW 2
S
T
A
R
J
P
C
IEEE1500
 Standard interface
 IEEE 1500 standard
interface between I-IP units
S
F
P
IW 3
STAR
ASAP
STAR
STAR
IW 4
6IW 3
ASAP
SRAMWRAPPER
2
WRAPPER 1
STAR
STAR
STAR
STAR
ASAP
RF
IW 6
6IW 4
SRAM
SRAM
STAR
STAR
ASAP
RF
WRAPPER 3
WRAPPER 4
STAR
SRAM
STAR
SRAM
21
Accelerating Silicon Debug Cycle
Bit Map
Tester
DB
SoC w/ ET&R
Std.
formant
NAS
Coordinate Identification
Silicon
Debug
Vector
Generation
22
Reducing Time to Debug
Allow accurate analysis -
• Identify defective memory
• Logical bit mapping
• Physical bit mapping
• Calculating X-Y coordinates
• Defect Classification
• Fault Localization – root cause identification
• Diagnosis – fault classification
NAS
23
Fault Type Diagnosis of Failed Bit
i) Single cell faults (SPF1)
 Stuck-at faults (SAF)
 Stuck-open faults (SOF)
 Transition faults (TF)
 Data retention faults (DRF)
 Read destructive fault
 Deceptive read destructive fault
 Incorrect read fault
ii) Two cell faults (SPF2)
 Inversion coupling fault (CFin)
 Idempotent coupling fault (CFid)
 State coupling fault (CFst)
 Disturb coupling fault (CFds)
 Incorrect read coupling Fault (CFir)
 Read destructive coupling fault (CFrd)
 Deceptive read destructive coupling Fault (CFdrd)
 Transition coupling fault
iii) Address decoder faults (AF)
NAS
24
Fault Classification
• Based on diagnostic information collected
from tester response, it will be possible to
determine fault types.
Example: March FD
(W0); (R0); (R0, W1, W1, R1); (R1, W0, R0, W1); (R1, W1);
(R1); (R1); (R1, W0, W0, R0); (R0, W1, R1, W0); (R0, W0);
(R0); (R0, W1, W1, R1); (R1); (R1, W0, W0, R0); (R0).
NAS
25
Part of Dictionary of MARCH FD
Example: SMS detected errors at (2, 3, 5, 6, 7, 8, 11,15, 16, 17)
Read operations then the fault is Stuck-At 0 (<1/0/->).
R R R R R R R R R R R R R R R R R R R R
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 17 18 19
<0/1/-> 1
1 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1
6
<1/0/-> 0 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 1 0 0
<0R0/1/ 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1
0>
<1R1/0/1
0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0
>
Each two pair of Fault signatures do not coincide
MARCH FD – Full Diagnosis algorithm
NAS
26
3. Trend: Embedded Memory in ICs
NAS
3. Enhancing Yield via Repair
1 Mb
2 Mb
4 Mb
8 Mb
16 Mb
24 Mb
32 Mb
100
90
Memory Yield (%)
80
70
60
Memory yield (without redundancy)
50
Memory Yield with redundancy
40
30
20
10
0
32.69
3
55.39
5
1110.78
11
2222
21.56
43
43
43.11
65
65
64.67
86
86
86.22
Width of die in mm
12.00
Height of die in mm
12.00
Defect density for logic
in # per sq. in.
0.4
Defect density for memory
in # per sq. in.
0.8
Process technology
32nm
% Memory
die
Percent
of Memoryon
on die
NAS
28
Conventional Manuf. Repair
 External Test & Repair Method
 Store failed bit map externally
in a large capture memory
 Use external general purpose
redundancy allocation
software
 Blow fuses using external
repair equipment
 High cost and silicon area
NAS
I-IP for Single Time Repair
•

External Memory tester
eliminated
 External bit map storage
eliminated
 External redundancy
analysis software eliminated
 High yield achieved
because of integrated
solution
NAS
Small
Capture
Memory
I-IP for Multi-Time Repair
 External repair
equipment eliminated
 Overall manufacturing
cost reduced
 Efficiency of repair
increased (PVT corner
conditions repaired)
 Efficient of area &
performance improved
NAS
Enhancing Yield via Repair
• Type and amount of redundancy
• Fault detection & location algorithm
• Redundancy allocation algorithm
• Repair Methodology
• Reconfiguration mechanism
NAS
32
Redundancy and Repair Allocation
 Repair Efficiency
depends on
– Knowledge of
memory topology
– Knowledge of
process defect
history
– Having dedicated
algorithms
NAS
4. Problem: Resource Limitation Challenge
• Cost of production increased
• Counterpoint: The San Andreas Fault
NAS
Globalization in Technology Production
• New locations around the world
– Manufacturing, ex: Mexico, Taiwan, China
– Development, ex: India, Korea
– Research, ex: Armenia, Russia
• New trends in global technology production
– Distributed corporate sites
– Outsourcing services
– New global start-ups
NAS
Top 20 Semiconductor Technology Companies
2007
Rank
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NAS
2006
Rank
1
2
4
3
5
7
6
14
10
15
8
16
11
9
13
12
17
19
18
20
Company
Intel
Samsung Electronics
Toshiba
Texas Instruments
STMicroelectronics
Hynix
Renesas technology
Sony
NXP
Infineon Technologies
AMD
Qualcomm
NEC Electronics
Freescale Semiconductor
Micron Technology
Qimonda
Matsushita Electric
Elpida Memory
Broadcom
Sharp Electronics
2006
Revenue
(Millions)
$
31,542
$
19,842
$
10,141
$
12,600
$
9,854
$
7,865
$
7,900
$
5,129
$
5,894
$
5,119
$
7,506
$
4,529
$
5,601
$
5,988
$
5,247
$
5,413
$
4,022
$
3,527
$
3,668
$
3,341
2007
Revenue
(Millions)
$
33,973
$
20,137
$
12,590
$
12,172
$
9,991
$
9,614
$
8,137
$
8,040
$
6,038
$
5,864
$
5,792
$
5,603
$
5,555
$
5,349
$
4,943
$
4,186
$
3,946
$
3,836
$
3,731
$
3,584
Percent
Change
7.7%
1.5%
24.1%
-3.4%
1.4%
22.2%
3.0%
56.8%
2.4%
14.6%
-22.8%
23.7%
-0.8%
-10.7%
-5.8%
-22.7%
-1.9%
8.8%
1.7%
7.3%
Global SOC Development
- Flat versus hierarchical design solutions
- Pre-optimized hard IP blocks made reusable
RF
RF
PLL
Flash
RF
DSP
Processor
Logic
NAS
Mega Bit
SRAM
SRAM
37
5. Trend: SOC/SiP Alternatives
•
SOC: System on Chip. Integrate combinations of logic,
processor, SRAM, DSP, A/RF, DRAM, NVM
•
SiP: Stacked ICs & Packages
1. Non-TSV
–
–
bare die stacking: wirebond, flipchip, embedded die substrate
package stacking: PoP, PiP
2. TSV
–
•
via first, via middle, via last
SOP: System on Package. Integrate passives, power
mgmt, thermal structures, antenna switches, MEMS,
etc.
NAS
SOC/SiP Tradeoffs
PRO
SOC
CON
High performance, low
power if tech optimum
IP instantiation for each tech
node & fab
Low cost if simple process
NRE cost
SOC and SiP Development time
Complex verification & test
arelevelcomplementary
Chip
miniaturization
Optimum technology for
Low chip-chip
and
co-exist
in
products
dissimilar functions
connectivity
Smaller Bill Of Materials
SiP
(without TSV)
Flexible reuse of components
Lack of EDA tools
Shorter Time to Market
KGD/test planning
Yield liability
NAS
Evolution in 3D Technologies
Current SiP (non-TSV)
TSS
Source: ChipPAC

Limitations
– Peripheral bonds only
– Long wire bonds (high inductance, high
crosstalk, low speed interconnect)
 Limited to low-density
interconnects and with
specific I/O pad routing
NAS

Benefits
–
–
–
Area placement
Excellent electrical characteristics
High densities
 Orders of magnitude
higher interconnect
densities between dies
Packaging scenarios for 3D Stacked DRAM
Board
DDR2 -16bit
Logic
PCB
SiP
DDR2 -16bit
PCB
3D TSS
(TSVs)
Existing DDR2
-16bit
Using an existing
DDR2 die
PCB
3D-ready
DDR2 -xbit
PCB
NAS
Wide Interface
DDR2 die
Thru Silicon Stacking
Multi-discipline Challenges & Gaps
• Supply Chain and Standardization
• Cost
• DFT/Test
– test strategy and circuits
– KGD
– failure analysis techniques
• Thermal/Mechanical/Reliability
• EDA tools and methodologies
NAS
6. Application-Specific Challenge
• Application-specific disaggregation of semiconductor
industry – similar to system houses
– Digital home, enterprise, portable, health, etc.
• Application-specific disaggregation of semiconductor
supply industry
– EDA suppliers
– IP providers
– Foundries
• Test, diagnostics, yield, reliability requirements for
each application domain
NAS
Application-Specific Solution
• What is the impact on Design & Test Technology
Graphics and
Computing
Portable and
Hand-held
Communications
and Networking
Consumer
NAS
Application-Specific Yield
NAS
Disruptive Technology
Imaging, Characterization, Analysis and Modification in
Three Dimensions Down to the Sub-Angstrom Level
NanoBiology
NanoResearch
Industry and Institute
“Energy creation engine”
inside a cell at NCI/NIH
46
NAS
Oil Refining
Catalyst
NanoElectronics
Semiconductor
Data Storage
Defect Analysis
Metrology
Scaling The NanoScale
Question? How many copper atoms
can be aligned on the diameter of a
penny?
Answer.
152 Million
A Copper atom is 0.125
nm in diameter
47
NAS
A Penny is 0.75”
diameter = 1.9cm
Properties Vary at Nanoscale
Nanoscale
Property scale
Atomic &
Molecular
Micro-macro-bulk
Gold ~1nm =
Semiconduct
or
Atomic
1nm
100nm
Properties: Electronic, Magnetic, Photonic, Catalytic, etc.
50
NAS
Bulk material
Industries Entering into Nanozone
Pharmaceuticals and Healthcare….
Nanobiology Business
Industries….
feature size
Data storage
NanoIndustry Business
Semiconductors
Nanoelectronics Business
100 nanometers
nanozone
Research is pervasive
time
51
NAS
Change and perception –
When does science fiction
Popular culture helps to drive consumer perception
• Cost Matters - ALWAYS
–
•
•
•
Smaller is better, bigger is obviously obsolete
Function and Quality Matter
–
–
–
–
–
Bi-directional video with mid to high range digital camera
Lifetime of music on my iPOD – or cell phone
Virtual surround sound with 3D Video and HDTV headsets
GPS
Wearable devices / voice controlled (accurate) input devices
Time to Market Matters because
–
Cyber gloves
Low end phones in 2000 ~ $150, today ~ $22 ( with better size and more features)
Size Matters –
–
meet science
When do I get my personal Tricorder? I want it NOW !!
NAS
Heads up
displays
Conclusion
Advanced products for new generations
Technology Miniaturization Continues !
Design & Test Challenges Continue !
Innovative Solutions Needed !
NAS
Thank You
NAS