Transcript ECE 601 - Digital System Design & Synthesis Lecture 5

ECE 551: Digital System
Design & Synthesis
Lecture Set 10
10.1: Functional & Timing
Verification (Separate File)
10.2: Faults & Testing
10.2 Appendix: PODEM Example
Slides adapted from ECE 553 Slides by Prof.
Kewal Saluja
04/23/2003
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ECE 551 - Digital System Design & Synthesis
Lecture 10.2 – Faults and Testing
Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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Introduction
The manufacturing process for ICs is so complex
that only a portion of all chips produced are
good – the percentage of such good chips is
referred to as the yield
 In order to avoid shipping defective products,
manufacturing test at the die and packaged chip
level is required.
 Complex chips => complex tests


The objective: summary the elements of
contemporary IC test
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Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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Common Fault Models
Single stuck-at faults
 Transistor open and short faults
 Memory faults
 PLA faults (stuck-at, cross-point,
bridging)
 Functional faults (processors)
 Delay faults (transition, path)
 Analog faults

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Stuck-at Faults
•Single stuck-at fault model
•What does it achieve in
practice?
•Fault equivalence
•Checkpoint faults
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Single Stuck-at Fault

Three properties define a single stuck-at fault
• Only one line is faulty
• The faulty line is permanently set to 0 or 1
• The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24
single stuck-at faults
Faulty circuit value
c
1
0
a
d
b
e
f
Good circuit value
j
s-a-0
g
1
0(1)
1(0)
h
i
z
1
k
Test vector for h s-a-0 fault
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Single Stuck-at Faults
(contd.)
How
effective is this model?
 Empirical evidence supports the
use of this model
 Has been found to be effective to
detect other types of faults
 Relates to yield modeling
 Simple to use
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Fault Equivalence
Number of fault sites in a Boolean gate circuit =
#PI + #gates + # (fanout branches).
 Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also detect f2.
 If faults f1 and f2 are equivalent then the
corresponding faulty functions are identical.
 Fault collapsing: All single faults of a logic circuit
can be divided into disjoint equivalence subsets,
where all faults in a subset are mutually
equivalent. A collapsed fault set contains one
fault from each equivalence subset.

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Equivalence Example
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
Faults in blue
removed by
equivalence
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
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Checkpoints
Primary inputs and fanout branches of a
combinational circuit are called checkpoints.
 Checkpoint theorem: A test set that detects all
single (multiple) stuck-at faults on all
checkpoints of a combinational circuit, also
detects all single (multiple) stuck-at faults in
that circuit.

Total fault sites = 16
Checkpoints ( ) = 10
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Summary






Gate level models are most prevalent in logic testing
Fault models are analyzable approximations of defects
and are essential for a test methodology.
For digital logic single stuck-at fault model offers
advantage of effective tools and much experience.
Many other faults (bridging, stuck-open and multiple
stuck-at) are largely covered by stuck-at fault tests.
Stuck-short and delay faults and technology-dependent
faults require special tests.
Memory and analog circuits need other specialized fault
models and tests.
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Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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Definition of Automatic
Test-Pattern Generator

Operations on digital hardware:
 Inject fault into sequential circuit modeled in computer
 Use various ways to activate and propagate fault effect
through hardware to circuit output
 Output flips from expected to faulty signal

Scan design – add test hardware to all flipflops to make them a giant shift register in
test mode
 Can shift state in, scan state out
 Widely used – makes sequential circuit into combinational
circuit for testing!
 Costs: 5 to 20% chip area, circuit delay, extra pin, longer
test sequence
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Notation
Failing
Good
Meaning
Machine Machine
Symbol
D
D
0
1
X
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1/0
0/1
0/0
1/1
X/X
1
0
0
1
X
0
1
0
1
X
Roth’s D
Algebra
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Conditions for Finding a
Test
Fault excitation – the signal value at the
fault site must be different from the
value of the stuck-at fault (thus fault site
must contain a D or a D)
 The fault effect must be propagated to a
primary output (A D or a D must appear
at the output)
 Some simple observations

 There must be at least a D or a D on some
circuit nets)
 D’s must form a chain to some output
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Exhaustive Algorithm
For n-input circuit, generate all 2n input
patterns
 Infeasible, unless circuit is partitioned
into cones of logic, with  15 inputs

 Perform exhaustive ATPG for each cone
 Misses faults that require specific activation
patterns for multiple cones to be tested
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Random-Pattern Generation
Flow chart
for method
 Use to get
tests for 6080% of
faults, then
switch to Dalgorithm or
other ATPG
for rest

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Path Sensitization Method Example 1 Fault
Sensitization
2 Fault
Propagation
3 Line Justification
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Path Sensitization Method Example
 Try path f – h – k – L. This path is
blocked at j, since there is no way to
justify the 1 on i
1
1
D
D
D
D
1
0
D
1
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Path Sensitization Method
 Try simultaneous paths f – h – k – L and
g – i – j – k – L. These paths blocked at k
because D-frontier (chain of D or D) disappears
1
1
D
D
1
D
D
D
1
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Path Sensitization Method
Circuit Example
 Final try: path g – i – j – k – L – test
found!
0
1
0
D
D
D
D
D
1
1
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Overview
Major ATPG algorithms
• Definitions
• D-Algorithm (Roth) – 1964-66
– D-cubes
– Bridging faults
– Logic gate function change faults
• PODEM (Goel) -- 1981
– X-Path-Check
– Backtracing
• Summary
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Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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Definition

Design for testability (DFT) refers to those
design techniques that make test generation
and test application cost-effective.
 DFT methods for digital circuits:
 Ad-hoc methods
 Structured methods:
•
•
•
•
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Scan
Partial Scan
Built-in self-test (BIST)
Boundary scan
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Scan Design
 Objectives
• Simple read/write access to all or subset of storage
elements in a design.
• Direct control of storage elements to an arbitrary
value (0 or 1).
• Direct observation of the state of storage elements
and hence the internal state of the circuit.
Key is – Enhanced controllability and observability.
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Scan Design
 Circuit is designed using pre-specified design rules.
 Test structure (hardware) is added to the verified design:
• Add one (or more) test control (TC) primary input.
• Replace flip-flops by scan flip-flops and connect to form one or
more shift registers in the test mode.
• Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all testable
faults in the combinational logic.
 Add shift register tests and convert ATPG tests into scan
sequences for use in manufacturing test.
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Scan Flip-Flop (masterslave)
Master latch
D
Slave latch
TC
Q
Logic
overhead
MUX
SD
CK
Q
D flip-flop
CK
TC
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Master open Slave open
Normal mode, D selected
t
Scan mode, SD selected
t
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Adding Scan Structure
PI
PO
Combinational
SFF
logic
SFF
SCANOUT
SFF
TC or TCK
SCANIN
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Not shown: CK or
MCK/SCK feed all
SFFs (scan Flipflops).
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Comb. Test Vectors
PI
I1
I2
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O2
Combinational
SCANIN
TC
Presen
t
state
O1
SCANOUT
logic
S1
S2
PO
N1
N2
Next
state
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Comb. Test Vectors
SCANIN
I2
I1
PI
S1
S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
PO
SCANOUT
Don’t care
or random
bits
1 0000000
O2
O1
N1
N2
Sequence length = (nsff + 1) ncomb + nsff clock periods
ncomb = number of combinational vectors
nsff = number of scan flip-flops
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Scan Overhead
IO pins: One pin necessary.
 Area overhead:

 Gate overhead = [4 nsff/(ng+10nff)] x 100%,
where ng = comb. gates; nff = flip-flops;
• Example – ng = 100k gates, nff = 2k flip-flops, overhead =
6.7%.
 More accurate estimate must consider scan wiring and
layout area.

Performance overhead:
 Multiplexer delay added in combinational path; approx.
two gate-delays.
 Flip-flop output loading due to one additional fanout;
approx. 5-6%.
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Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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BIST Process


Test controller – Hardware that activates self-test
simultaneously on all PCBs
Each board controller activates parallel chip BIST
Diagnosis effective only if very high fault coverage
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BIST Architecture

Note: BIST cannot test wires and
transistors:
 From PI pins to Input MUX
 From POs to output pins
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Pattern Generation

Store in ROM – too expensive
Exhaustive
 Pseudo-exhaustive
 Pseudo-random (LFSR) – Preferred

method
 Binary counters – use more hardware
than LFSR
 Modified counters
 Test pattern augmentation
 LFSR combined with a few patterns in ROM
 Hardware diffracter – generates pattern
cluster in neighborhood of pattern stored in
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ROM
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Exhaustive Pattern Generation (A
Counter)



Shows that every state and transition works
For n-input circuits, requires all 2n vectors
Impractical for large n ( > 20 )
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Random Pattern Testing
Bottom:
RandomPattern
Resistant
circuit
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Pseudo-Random Pattern
Generation

Standard Linear Feedback Shift Register (LFSR)
 Normally known as External XOR type LFSR
 Produces patterns algorithmically – repeatable
 Has most of desirable random # properties
 Need not cover all 2n input combinations

Long sequences needed for good fault coverage
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Test Pattern Augmentation

Secondary ROM – to get LFSR to 100%
SAF coverage
 Add a small ROM with missing test patterns
 Add extra circuit mode to Input MUX – shift to
ROM patterns after LFSR done
 Important to compact extra test patterns

Use diffracter:
 Generates cluster of patterns in neighborhood
of stored ROM pattern
Transform LFSR patterns into new vector
set
 Put LFSR and transformation hardware in
full-scan chain
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
Response Compaction

Severe amounts of data in CUT response to
LFSR patterns – example:
 Generate 5 million random patterns
 CUT has 200 outputs
 Leads to: 5 million x 200 = 1 billion bits
response
Not economical to store and check all of
these responses on chip
 Responses must be compacted

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Definitions




Aliasing – Due to information loss, signatures of
good and some bad machines match
Compaction – Drastically reduce # bits in original
circuit response – lose information
Compression – Reduce # bits in original circuit
response – no information loss – fully invertible
(can get back original response)
Signature analysis – Compact good machine
response into good machine signature. Actual
signature generated during testing, and
compared with good machine signature
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LFSR for Response Compaction



Use cyclic redundancy check code (CRCC) generator
(LFSR) for response compacter
Treat data bits from circuit POs to be compacted as a
decreasing order coefficient polynomial
CRCC divides the PO polynomial by its characteristic
polynomial
 Leaves remainder of division in LFSR
 Must initialize LFSR to seed value (usually 0) before testing


After testing – compare signature in LFSR to known
good machine signature
Critical: Must compute good machine signature
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Example Modular LFSR
Response Compacter

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LFSR seed value is
“00000”
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Summary
LFSR pattern generator and MISR response
compacter – preferred BIST methods
 BIST has overheads: test controller, extra
circuit delay, Input MUX, pattern generator,
response compacter, DFT to initialize circuit
& test the test hardware
 BIST benefits:







At-speed testing for delay & stuck-at faults
Drastic ATE cost reduction
Field test capability
Faster diagnosis during system test
Less effort to design testing process
Shorter test application times
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Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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Overview: Boundary Scan
Motivation
 System view of boundary scan
hardware
 Elementary scan cell
 Test Access Port (TAP) controller
 Boundary scan instructions
 Summary

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Motivation for Standard
n
Bed-of-nails printed circuit board tester gone
 We put components on both sides of PCB & replaced DIPs
with flat packs to reduce inductance
n Nails would hit components
 Reduced spacing between PCB wires
n Nails would short the wires
 PCB Tester must be replaced with built-in test delivery
system -- JTAG does that
 Need standard System Test Port and Bus
 Integrate components from different vendors
n Test bus identical for various components
n One chip has test hardware for other chips
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System Test Logic
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System View of Interconnect
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Boundary Scan Chain View
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Elementary Boundary Scan
Cell
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Tap Controller Signals
n
Test Access Port (TAP) includes these signals:
 Test Clock Input (TCK) -- Clock for test logic
Can run at different rate from system clock
Test Mode Select (TMS) -- Switches system
from functional to test mode
Test Data Input (TDI) -- Accepts serial test
data and instructions -- used to shift in
vectors or one of many test instructions
Test Data Output (TDO) -- Serially shifts out
test results captured in boundary scan chain
(or device ID or other internal registers)
Test Reset (TRST) -- Optional asynchronous
TAP controller reset
n




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Tap Controller State Diagram
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EXTEST Instruction
n
Purpose: Test off-chip circuits and boardlevel interconnections
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Summary
n
Boundary Scan Standard has become
absolutely essential - No longer possible to test printed circuit
boards with bed-of-nails tester
 Not possible to test multi-chip modules
at all without it
 Supports BIST, external testing with
Automatic Test Equipment, and
boundary scan chain reconfiguration as
BIST pattern generator and response
compacter
 Now getting widespread usage
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Overview
Introduction
 Fault Models
 Test Pattern Generation
 Design for Testability (DFT) – Serial Scan
 Built-In Self-Test (BIST)
 Boundary Scan (JTAG/IEEE 1149.1)
 Quiescent Drain Current (IDDQ) Testing

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Basic Principle of IDDQ
Testing
 Measure IDDQ current through Vss bus
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Stuck-at Faults Detected by
IDDQ Tests

Bridging faults with stuck-at fault behavior
 Levi – Bridging of a logic node to VDD or VSS – few
of these
 Transistor gate oxide short of 1 KW to 5 KW

Floating MOSFET gate defects – do not fully
turn off transistor
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NAND Open Circuit Defect
– Floating gate

The fault
manifests as
stuck-at, weak
ON for N-FET,
or delay fault
some
manifestations
can be tested
by IDDQ tests
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Floating Gate Defects
 Small
break in logic gate inputs (100 –
200 Angstroms) lets wires couple by
electron tunneling
 Delay fault and IDDQ fault
 Large
open results in stuck-at fault – not
detectable by IDDQ test
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Bridging Faults S1 – S5



Caused by absolute short (<
50 W) or higher R
Segura et al. evaluated
testing of bridges with 3
CMOS inverter chain
IDDQRb tests fault when
Rb > 50 KW or
0  Rb  100 KW

Largest deviation when Vin =
5 V bridged nodes at opposite
logic values
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Delay Faults
Most random CMOS defects cause a timing
delay fault, not catastrophic failure
 Many delay faults detected by IDDQ test – late
switching of logic gates keeps IDDQ elevated
 Delay faults not detected by IDDQ test

 Resistive via fault in interconnect
 Increased transistor threshold voltage fault
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Leakage Faults
 Gate
oxide shorts cause leaks between gate
& source or gate & drain
Weak Faults
• nFET passes logic 1 as 5 V – Vtn
• pFET passes logic 0 as 0 V + |Vtp|
• Weak fault – one device in C-switch does not turn on
 Causes logic value degradation in C-switch
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Transistor Stuck-Closed
Faults
Due to gate oxide
short (GOS)
 k = distance of short
from drain
 Rs = short resistance
 IDDQ2 current results
show 3 or 4 orders of
magnitude elevation

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Gate Oxide Short
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IDDQ Summary

IDDQ tests improve reliability, find defects
causing:
 Delay, bridging, weak faults
 Chips damaged by electro-static discharge

No natural breakpoint for current threshold
 Get continuous distribution – bimodal would be
better


Conclusion: now need stuck-fault, IDDQ, and
delay fault testing combined
Still uncertain whether IDDQ tests will remain
useful as chip feature sizes shrink further
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