Transcript Chapter10

Physical Memory
And
Physical Addressing
Chapter 10
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RAM Technologies
• RAM is used as primary memory in many
computer systems, it provides random
access, it can be updated and is volatile.
• The two technologies used to implement
RAM are – SRAM (Static RAM)
- DRAM (Dynamic RAM)
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SRAM
• It is an extension of digital logic.
• SRAM uses a flip flop(4 to 6 transistors) to
store a bit
• Very fast
• Consume a lot of power
• Larger than DRAM, so less density
• Typically used for memory applications
that are small but fast.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
DRAM
• DRAM use a capacitor to store a charge
representing if it is set or cleared.
• Capacitors are smaller than flip flops, so it can be
more densely packed
• Slower than Flip Flops
• Low cost, low power, high density(small package) ,
high speed.
• DRAM has been the standard RAM used in all
computers.
• DRAM can be found in every thing, from
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automobiles to automatic bread maker
Problems with DRAM
• There is problem with DRAM , the
capacitors discharge and the bits become 0.
• DRAM contains extra circuit for refresh,
refresh circuit.
• The circuit performs task of reading and
then writing a bit back.
• The hardware must ensure that the value of
a bit does not change between the read and
write operation of the refresh circuit.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Illustration of a memory module
with DRAM Chips
• DIMM
• Dual In Line Memory Module
• Type of popular RAM module
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Measures Of Memory Technology
• The quantitative measures to assess memory
technology are
1 - Density
2 - Latency And Cycle times (Speed)
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1-Measures Of Memory Technology
Chip Density: Each memory chip is a matrix of tiny cells.
• Each cell holds one bit of information.
• The Number of bits which can be held in a chip is defined
as chip density. Higher density is desirable but chip require
more power and generate more heat.
• Chip density is measured in megabits (Mbit).
• Ex: A 64Mbit chip has 64 million cells and is capable of holding 64 million bits of
data
• In DRAM chips the density is expressed as
the depth of the chip (in locations) x width of the chip (in bits)
Ex: 4M x 16 = 64 Mbit ; 4 is depth of chip in millions of locations(rows)
16 is the width of the chip in bits(columns)
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1-Measures Of Memory Technology(con’)
CALCULATING THE CAPACITY OF A MODULE:
• A module consists of a group of chips
• Adding the capacities of all the chips on the module gives the total
capacity of the module.
• The capacity of a module is described in megabytes
• Exercise: If I have a memory module with 8 DRAM Chips and
the Chip Density is 64 Mbits , how much memory do I have .
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1-Measures Of Memory Technology(con’)
• Sol:
No. of DRAM chips in my module = 8
Density of each chip = 64 Mbit
Capacity of the Module = 64 x 8 = 512Mbit
Capacity is described in Megabytes(MB)
512Mbits
= ------------------ = 64 MB Module
8 bits per byte
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2-Measures of performance
• Speed : refers to how quickly the memory
system can handle successive requests.
• The amount of time that RAM takes to write
data or to read it when it receives a request
from the processor is called the access time
• Access time consists of Latency and transfer
time
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
HOW MEMORYWORKS WITH THE PROCESSOR
Memory
bus
North Bridge &
South Bridge
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2-Measures of performance (cont’)
• Latency is the time elapses between a start of an operation
and end of an operation.
or
The overhead of finding the right place for the memory
access and preparing to access it.
• Transfer time is the time required between successive
operations.
• Time taken for write operations might differ significantly
from the time taken for read operations.
• Hence the engineers use two separate measures :the read
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cycle time (tRC) and write cycle time (tWC)
Types of RAM
• Asynchronous RAM : works with the
system speed
• Synchronous RAM : works with the speed
of the Processor.
- SSRAM(synchronous static RAM)
-SDRAM(synchronous dynamic RAM)
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Types of RAM technologies
mostly used
• FPM RAM obsolete
• SDRAM
• DDR SDRAM
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SDRAM
• SDRAM: Synchronous DRAM (DRAM is asynchronous).
• SDRAM is designed to synchronize itself with the timing of
the CPU.
• This enables the memory controller to know the exact clock
cycle when the requested data will be ready, so the CPU no
longer has to wait between memory accesses.
• The RAM speed had to match or exceed system speed or
the computer would be unstable or would not wok at all .
• PC100 SDRAM runs at 100MHz, PC133 SDRAM runs at
133MHz.
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• Common size on desktops: 168-pin DIMM
DDR SDRAM: Double data rate
synchronous dynamic RAM
• DDR RAM was developed from SDRAM technology
• It doubles the throughput of SDRAM by making 2
processes for every clock cycle.
• Runs at 200, 266, 333 …. 600 MHz
• DDR RAM uses 184-pin DIMMs that are different from
SDRAM DIMMs. They will not fit in the same socket.
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Memory Access & Memory Bus
• Memory Bus: The Hardware connection between
the processor and memory is called Memory bus
or Front side bus.
• It is a parallel connection consisting of several
wires.
• Each wire in the bus carry one bit of data.
• Parallel connection from a programmer’s point of
view defines the memory transfer size i.e. the
amount of data which can be read or written to a
memory in a single operation.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
MEMORY ADDRESSING
• The generic term for the smallest unit of memory that the
CPU can read or write is cell
• Hardware-accessible units of memory larger than one cell
are called words
• Currently (1998) the most common word sizes are 32 bits
(4 bytes) and 64 bits (8 bytes)
• Hence two schemes to address memory are :
- Byte addressing
- Word Addressing
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Byte Addressing
• Byte addressing refers to hardware architectures
which support, accessing individual bytes of data
• Memory is organized as an array of bytes
• This scheme is convenient to the programmers , it
helps to access small data items like characters.
• Each byte of memory is assigned an Address,
byte address.
• It allow a programmer to read/write a single byte,
hence the memory controller support byte
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transfer.
Word Addressing
• A block of N bits is grouped as a word, N is the
memory transfer size or Word size.
• Memory is organized as an array of words.
• It denotes the number of bits that a CPU can
process at one time.
• Each word of the physical memory is assigned a
unique number known as the physical memory
address.
• Every read/write operation applies to an entire
word.
• This architectural approach is known as word
addressing.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Word Size And Other Data Types
• When choosing the size of a word an architect has to
consider two important criteria
- the performance of the memory system
- its cost.
Performance:
• The word size should be able to accommodate common
data values (integers) , frequently used instructions.
• If for example a word size of 32 bits is chosen then the
architect will make the standard integer and the single
precision also occupy same place( since all parts of the
system work together)
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Word Size And Other Data Types
(cont’)
Cost:
• Bigger the word size higher the performance.
• But in contrast parallel hardware occupies
more space and increases the cost.
Thus the word size is chosen as a compromise
between the performance and economic costs.
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Byte Addressing With Word Transfers
• A memory system that offers Byte Addressing
gives lower performance than word addressing.
• Thus the a memory system that combines both
the approaches is devised.
• Controller accepts the byte addresses from the
processor , reads the appropriate word and
extracts the specified byte.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Using Powers Of Two
• Extra hardware (ALU) is required for
performing a division or computing a reminder.
• Memory is organized as powers of 2.
• Hardware can perform the computations by
extracting bits.
• N=2^2 , offset can be computed by extracting
two lower order bits and word address by
extracting rest of the bits.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Byte Alignment And Programming
• Byte Alignment is the way data is arranged and accessed in
computer memory.
• Ex. An integer value is aligned if the bytes for the integer
correspond to a word else it is termed as unaligned.
• Unaligned access result in lower performance because the
memory controller must perform two read operations to obtain
the requested bytes.
• Thus organization of physical memory affects performance.
• Data padding or aligning data on boundaries that correspond to
the physical word size can improve program performance.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Memory size and Address space
• Given a fixed Address size the amount of memory
which can be addressed depends whether the
processor uses byte addressing or word addressing.
• Further if word addressing is used the amount of
memory depends on the word size.
• Ex: On a system with word addressing where
4 bytes= Word
32 bit value can hold address for
17,179,869,184 bytes which is four times as much
as when using byte addressing.
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Programming with Word Addressing
• Byte addressing provides convenient interface to the
programmers, does not maximize the memory size
• Word Addressing provides access to maximum amount
of memory for a given address size.
• In a processor which uses word addressing . Software
acts as a controller.
• Software reads/writes a byte by locating the appropriate
word.
• The performance of the software is optimized by
performing logical shifts and bit masking on an address
rather than division or reminder computation.
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Pointers And Data Structures
• The C programming language has a heritage for both byte
and word addressing.
• An Example of byte pointer declaration
char *cptr;
The statement declares variable cptr to be a pointer to a
character (byte in memory)
• An Example of word pointer declaration
int *iptr;
The statement declares variable iptr to be a pointer to an
integer( word in the memory)
• If each integer contains four bytes, the autoincrement
statement
iptr++;
This increments the value of iptr by four. Moves to the next
word in memory.
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Memory Dump
• Example of a linked list.
• Each pointer in the list corresponds to a memory address
Head
192
200
100 ^
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Memory Dump (cont’)
• Each node in the shown list contains : an integer
count and a pointer to the next node on the list.
• In C, a node has the following Structure:
struct node {
int count;
struct node *next;
}
• Variable named Head is defined as head of the
list:
struct node *head;
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Memory Dump (Cont’)
• In the above example the processor uses byte
addressing.
• Grouping outputs into 4 byte units implies that the
underlying word size is 4 bytes(32bits).
Indirection & indirect operands: an instruction with an
immediate operand value of 0x1be1f specifies
indirection.
• The final operand value will be 6 according to the
memory dump example.
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Memory Banks And Interleaving
• Interleaving is another optimization technique used with
physical memory systems.
• Like memory banks, high is performance achieved through
hardware parallelism.
• The processor connects to multiple memory banks that each has
its own controller.
• Higher performance results from simultaneous operation.
• The controller is designed so that all banks operate
simultaneously.
• Interleaving is hidden from programmers.
• Programmer accesses contiguous bytes of memory(e.g. to fetch
an integer), hardware automatically divides the request into the
underlying memory modules.
• N -way interleaving is used to describe the number of memory
modules .
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Content Addressable Memory
• CAM: This form of memory includes hardware for high
speed searching.
• Each row which is used to store an item is called a slot.
• The memory is organized as a two dimensional array
• A processor specifies a search key which the CAM
hardware compares against each slot.
• A search key is same as the size of a slot.
• The CAM hardware compares the key with each slot .
• Hence finds an exact match.
• All the slots operate in parallel, hence time required to
perform the search does not depend on the number of slots.
• CAM is used when look up speed is more important than
cost.
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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. © 2005 Pearson Education, Inc. All rights
Key Points
•
•
•
•
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Two aspects of physical memory: technology, Organization.
Programmers find byte addressing convenient.
Word addressing enhances performance.
Memory controller translates byte address into word address.
A memory dump shows the contents of memory along with the
memory addresses of each location.muddassir
• Memory dump is used to relate data structures in a program to
values in memory at run time.
• CAM combines memory technology and memory organization.
CAM organizes memory as array of slots, provides high speed
search.
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