Transcript Slide 1

VLSI for 3D Integration:
Modeling, Design and
Prototyping
Neil Goldsman
Bruce Jacob
George Metze
Omar Ramahi
Mike Khbeis, Akin Akturk, Zeynep Dilli, Xi Shao, Latise Parker
Problems with Conventional 2D Multi-Chip Integration
The parasitics of
the bond pads,
wires and board
buses limit speed,
driving capability
and functionality
Chip-to-chip
PCB
integration
is limiting:
Bond Wire
Bond Pad
Transmission Line
Pins
IC 1
IC 2
Input
Output
Transmission Line
3-D Integration
3-D Chip Stacking (die stacking):
Bringing bare dies together
in a vertical structure.
Advantages:
-Enable more mixed signal integration
-Increased ratio of active Si substrate area to chip footprint area
-Reduction of delay, faster clock speeds and higher bandwidths, through
-Less use of pads, smaller pads
-Shorter interconnects
-Less parasitic impedance
Disadvantages:
-Potential increase in heat dissipation problems
-Increased (geometric, computational, routing) design complexity.
Research Goals:
-Develop prototypes and design tools to understand limits of 2D integration
and exploit benefits of 3D integration.
Outline
• Task I: Modeling and Prototyping Device
and Chip Heating for 2D & 3D Integration
• Task 2: Modeling and Prototyping for on
Chip Electromagnetic Effects
• Task 3: Prototyping and Modeling Passive
3D Structures
Task I: Coupled Modeling of Time-Dependent
Full-Chip IC and Quantum Non-Isothermal
Device Operation
Pentium III
Pentium III Temperature
Motivation :
• As devices get smaller on-chip thermal effects become increasingly
important.
• Predictions indicate that chip temperatures will increase exponentially
beyond acceptable values.
• Thus modeling of full-chip heating is essential for the design of fail-safe
architectures in both 2D and 3D.
Objective :
• Develop heating models for 2D and 3D IC’s.
• Predict circuit and chip performance variations due to chip heating.
• Test the model and develop temperature sensors by fabricating specially
designed chips.
Functional Blocks in Pentium III
0 Bus Interface Unit
1 Clock
2 L1 Data Cache
3 Memory Order Buffer
4 Execute
5 L2 Data Cache
6 Register Alias Table
7 Issue
8 Fetch
9 Decode
Source: www.intel.com
% Area
4.25
1.00
12.5
3.25
9.45
29.75
3.25
9.45
12.5
14.6
% Power
6.2
5.2
9.8
4.7
13
8.5
4.7
14.1
16.8
17.2
Thermal Network Containing Millions of Nodes
KCL-type lumped thermal network
Pentium has 40 million nodes
MOSFET devices and their thermal connections
Device Equations
d 2 ( y)
E ( y)   * 2  q ( x, y) ( y)
2m dy
2
q
     p  n  D

n 1
 .J n  Rn  Gn
t q
p 1
  .J p  Rp  G p
t q
2
T
C  . T    J n  J p  
t
Schrödinger Eqn.
Poisson Eqn.
Electron Current Continuity Eqn.
Hole Current Continuity Eqn.
Heat flow Eqn.
Integrated Circuit Heat Flow Equation
C
V
T
dV    TdS   HdV
t
S
V
 ij xij yij
Ti
i Ci

Ti  T j    HdVi

t
zij
j
Vi
C  C
th
Cith, j
k
k 1
T

T
 i, j i, j 
t

z
R 
xy
k
k 1
T

T
 i, j i, j 1 
Rith, j 1/ 2
th

k
k 1
T

T
 i, j i 1, j 
Rith1/ 2, j

Ti ,kj
Rith, j
 I ith, j Ti ,kj 
Flowchart
Coupled Flowchart
Device Simulations
MOSFET IV Curves for T=300K and 400K; VGS=0.4, 0.7, 1.0V
Temperature profile in the channel of a MOSFET; Far left and right
corners are source and drain sides, respectively. Far side is parallel
to gate terminal.
Chip Simulations & Cooling with Thermal Contacts
Maximum chip temperature for different
Temperature profile for a 0.5cm IC with uniform device counts with constant power density.
device activity throughout the chip: Temperature
Isotherms range from 300K at the chip edges to
360K inside chip.
Thermal contacts cool chip
Maximum chip temperature as a
function of uniformly distributed thermal
contacts.
Calculated Temperature Profile for Pentium III
Calculated Pentium III Temperature Profile with non-uniform device
activity throughout the chip but with uniform device activity within each
functional block:
• Temperature Isotherms range from 300K at the chip edges to 340K
inside the clock.
• Clock and L2 Cache are the hottest and coolest regions, respectively.
Prototyping Temperature Sensor Array (10x10)
Diodes are used as temperature
sensors:
Diode current increases
exponentially with temperature.
Task II: Modeling metal
and Measuring the Effects of
EM Parasitics and
Coupling in 2D and 3D
SiO
Microelectronic Circuits
2
Problems with Conventional 2D Multi-Chip Integration
The parasitics of
the bond pads,
wires and board
buses limit speed,
driving capability
and functionality
Chip-to-chip
PCB
integration
is limiting:
Bond Wire
Bond Pad
Transmission Line
Pins
IC 1
IC 2
Input
Output
Transmission Line
Effect of Pads
Designed chips with two different ring-oscillators:
1. “External”: Uses bonding pads for stage-to-stage connection
2. “Internal”: Stages directly connected to each other
Effect of Pads: Results Summary
Factor of ~ 800 Faster without Pads & PCB Connections
0.6 m chip, measurements taken by Tektronix oscilloscope with
1 pF-capacitance active probe on the breadboard
Internal Osc.
External Osc.
One-stage delay
112 MHz (31-stage)
(equivalent to 1.16
GHz for 3 stages)
398 KHz (11-stage)
(equivalent to 1.46
MHz for 3 stages)
~330 ps for internal,
~330 ns for external
devices
Speed ratio: 794.5
Load ratio: ~1000
Expecting similar results on a PCB
Effects of EM Coupling in IC
Noise Injection:
• Capacitive Injection
• Hot Electron Injection
n+
Csb
Noise Coupling
• Resistive Coupling
• Inductance Coupling
n+
Rhe
Noise Reception
• Capacitive Reception
• Threshold Voltage Modulation
n+
Cdb
Rsub
Csb
n+
Vth
Cdb
Output
Driver
Output
Driver
VCO
PFD
12-Bit Counter
IC Chip Layout
VCO
VCO
Output
Driver
Digital Switching Noise Testing Circuit 1
Coupling Measurement
Frequency:
Phase
Noise:
50MHz
100MHz
500MHz
-1.5dBc/Hz
-1.8dBc/Hz
-2.2dBc/Hz
35.4dBc/Hz
29.1dBc/Hz
12.8dBc/Hz
Modeling Interconnects and Coupling:
Maxwell’s Equation
B
 E  
t
Metal
 B 
Substrate
Insulator
r E
c
2
t
(1)
 J
J  E
Challenges:
• Skin depth effect in the metal layer.
• Substrate current.
• How to couple large EM wavelength (mm to cm)
scale with fine material structure (of um scale)?
• Ans. Develop new EM ADI Maxwell Solver
(2)
(3)
Simulating EM Coupling between Interconnect Lines in
Metal-Insulator-Silicon-Substrate (MISS) Structure
Voltage Pulse Coupling Results
Adjacent Interconnects X-section
555 um
6
um
20
um
Passive Vacuum
metal line
6
um
555 um
Active
metal line
500
um
1.8 um
2 um
SiO2
y
z
Lossy Silicon Substrate
500
um
x
Results: New simulator allows for resolving large variations in grid points
Induced voltage 20% of applied signal even at 20μm apart.
555 um
6
um
20
um
Passive Vacuum
metal line
Simulations show extensive
coupling through substrate
currents.
6
um
555 um
Active
metal line
1.8 um
2 um
SiO2
y
z
Lossy Silicon Substrate
x
Substrate Current:
Horizontal x-section
500
um
Substrate Current:
Vertical x-section
500
um
Task 3: Prototyping and
Modeling 3D Structures
3-D Connections
Chip-to-chip communication between different chips with vertical
vias that require 12m x 12m metal pads
Cadence-extracted capacitance for a pad 9.23 fF: Same order of
magnitude as inverter load cap
To be investigated: Extra capacitive effects of the vertical via
in2
out1
out2
in1
3-D Connections: “Symmetric” Chip
New chip in fab
with structures
that can be
connected in 3D
and planar
counterparts for
comparison
Planar inductor vs. Multilayer
inductor
Layouts for planar inductor (left) and multilayer inductor (right), in
fabrication for probe-station measurements. The total length of the
inductors are the same, and the two pictures are of the same scale.
Note the much smaller footprint of the multilayer inductor.
Modeling Inductance
Net inductance represented
by inductance matrix:
•Diagonal elements: selfinductances of segments
•Off-diagonal elements: mutual
inductances between segments
 V1   L11 Lm,12
V   L
L22
 2    m, 21
  

  
VN   Lm, N 1 Lm, N 2
 Lm,1N   I 

 Lm,1N   I 
 s 
   
  
 LNN   I 
Mutual inductance calculation: The vector potential approach
Lm,ij




1


4 ai
i ai
J j dai da j
rij
j aj

aj
J j da j
d li  d l j
Planar Inductor vs. Multilayer
Inductor
Same net length  same net resistance, but higher inductance.
(four-level multilayer)
Conclusion:
•
•
•
•
•
A methodology was developed to model full-chip heating.
Predictions show thermal coupling between devices causes
the chip heating.
Excessive heating will render circuits inoperable.
Careful placement of micron-scale thermal contacts should
relieve the problem.
To test our methodology and develop new technology, we
designed a chip and submitted it to MOSIS for fabrication.
Conclusion:
• Prototyped chips show 30dBm in 2D EM noise coupling
• An Electromagnetic Solver was developed that is tailored to
IC’s
• The method can be used to resolve the coupling between large
EM wave length and fine material structure, e.g. IC on-chip
interconnects.
• Show the dispersion and decaying of the signal propagating
along the Metal Insulator Semiconductor Substrate (MISS)
structure.
• Show the detailed structure of the electric and magnetic field
inside the metal and substrate. The substrate current can lead
to cross-talk and losses.
• In the skin-effect mode region, enhancing the silicon substrate
doping conforms the shape of propagating signal better.
Conclusion:
• Prototyping shows bonding pads and I/0 ESD protection
circuits can cause 800 times decrease in circuit operation
speed.
• 3D integration will obviate need for most I/0 circuits reducing
delays.
• Chip modules for 3D integration developed.
• 3D inductors designed and under fabrication.
• Modeling indicates 3D inductors yield superior performance to
2D counterparts.
Future Work
• Incorporate heat sensor into 3D structures and calibrate heat
model.
• Incorporate heat conduits into 3D structures.
• Expand EM calculations to 3D interconnects and more passive
structures.
• Test fabricated inductor structures to experimentally to verify
advantages of 3D.
• Perform 3D stacking of 2D MOSIS chips.
• Develop state-of-the-art mixed signal 3D IC.