Transcript 60 GHz wirless receiver frontend on 90 nm CMOS
A 1.2V, 60-GHz radio receiver with on-chip transformers and inductors in 90-nm CMOS 28th IEEE Compound Semiconductor Symposium David Alldred Brian Cousins Sorin Voinigescu University of Toronto Overview 1. 2. 3. 4. 5. 6. Motivation Circuit blocks and schematics Passive element design Layout and fabrication Measurement results Conclusion Motivation Why 60-GHz radio? • Enough bandwidth for 2+Gb/s data transmission • Simpler radio architecture • Smaller die (lower cost?) than at 2-10 GHz. Why CMOS? • 90-nm MOSFETs have fMAX > 200 GHz at 1V supply and 0.2mW/mm • 90-nm n-MOSFETs have similar NFMIN as 200-GHz SiGe HBTs • For large volume applications CMOS can be the lowest cost solution ISCAS-07 Goal RFIC-06 CSICS-06 Wireless Transceiver System • Design and test receiver subsystem in digital CMOS • Operating frequencies: RF: 60GHz, LO: 55GHz, IF:5 GHz • Maximize Receiver Figure of Merit: f * G * IIP3 FoM ( F 1) * P Downconverter Block Diagram • Fully differential core except mm-wave interfaces • Two on-chip 60-GHz baluns for SE-Diff. conversion Circuit Blocks: LNA • • • • Two-stage cascode with middle inductor for NFMIN, S21 Biasing at 0.15 mA/mm ensures minimum noise in LNA LVT devices to ensure operation from 1.2 V supply Ported from 1.5V design in 90nm RF CMOS by T.Yao et al. RFIC-2006 Circuit Blocks: Mixer • Double-balanced Gilbert cell for LO-RF leakage • Design strategy: minimize noise, maximize linearity • CM inductor for noise and headroom • Middle inductors increase gain and reduce noise • Interdigitated diff-pair layout sharing well Circuit Blocks: LO buffer, IF buffer LO Buffer Output Buffer • Differential CS topology for simplicity • LO buffer designed as CML gate for fast switching • IF buffer @ 0.3mA/mm for maximum linearity (determines receiver linearity and drives 50-Ohm loads) Passive Element Design Inductors 2π inductor model Vertically-stacked inductor • Y-parameters from field solver (ASITIC) • Broadband 2π-model extracted from simulated Y-params • Skin effect included for 55GHz and 60GHz inductors Passive Element Design Balanced single-to-differential converter Balun model schematic Layout of verticallycoupled, two-layer balun • Balun model adapted from inductor π-model • Mutual capacitances distributed for balanced operation Fabrication • • • • 90nm GP CMOS (STM) 7M digital back-end LVT transistors fT/fMAX = 125/240 GHz 600x475 μm including all pads Receiver Measurement Results • • • • RF = 60 GHz, IF = 5 GHz VGS for min. NF50 is slightly below peak gain (fMAX) bias Confirms Jopt =0.15 - 0.2 mA/mm even at 60 GHz IF bandwidth is > 2 GHz centered at 4.5 GHz Conversion Gain, S11 vs. RF freq. • • • • Peak gain of 21 dB at 52 GHz Coincides with center frequency of S11 Input LNA inductor LG was 10% too high Re(Zin) = 50 W @ 60 GHz. Supply variation and LO power • Operation verified over 1.1V to 1.5V range • Noise Figure and Gain saturate for LO power > 2dBm Linearity and LO-RF leakage Performance Summary Simulation Results Parameter Measured Simulated Frequency 60 GHz 60 GHz Power Gain 16-20 dB 21 dB NFMIN 5.5-7 dB 7.4 dB P1dB -21 dBm -20 dBm IIP3 - -11.3 dB Pdiss 60 mW 62.5 mW Isolation (LO-RF) < -94 dB -120 dB Area 0.6x0.48 mm2 0.6x0.48 mm2 • Results are very close to simulated value • 6 dB lower NF than similar design in 150GHz SiGe BiCMOS [M. Gordon, SiRF-06] but no on-chip VCO Conclusion • 60 GHz wireless receiver is feasible in 90 nm GP CMOS • LVT devices critical for low-voltage/low-power • Thick copper back-end was NOT critical • Similar NF and P1dB to SiGe HBT technology but lower power • Mixer and LNA consume only 20 mA (24 mW) • Power could be further reduced with integration (buffers) • Ultra small area of 0.28mm2 because of inductors Acknowledgments • CMC for fabrication and CAD tools • Keith Tang and KenYau for help with measurements • OIT, CFI and ECTI for equipment Thank you for your time.