Transcript Slide 1

EET 252 Unit 4
Programmable Logic: SPLDs & CPLDs
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Read Floyd, Sections 11-1 to 11-4.
Study Unit 4 e-Lesson.
Do Lab #4.
Homework #4 and Lab #4 due next
week.
Quiz next week.
Programmable Logic
Programmable Logic Devices (PLDs) are chips with a large
number of gates and flip flops that can be configured with
software to perform a specific logic function or perform the
logic for a complex circuit. Major types of PLDs are:
SPLD (Simple PLD): the earliest type of array logic used for fixed
functions and smaller circuits with a limited number of gates. (The
PAL and GAL are both SPLDs).
CPLD (Complex PLD): contain multiple SPLD arrays and interconnection arrays on a single chip.
FPGA (Field Programmable Gate Array): a more flexible
arrangement than CPLDs, with much larger capacity.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Programmable Logic
Advantages of PLDs over fixed-function chips include
 Reduced complexity of circuit boards
• Lower power requirements
• Less board space
• Simpler testing procedures
 Higher reliability
 Design flexibility
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Approximate Equivalent Densities
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The Lattice GAL22V10 (a popular
SPLD) is equivalent to about 500 logic
gates.
A typical Altera MAX7000 CPLD is
equivalent to about 2500 logic gates.
A typical Altera Cyclone FPGA is
equivalent to about 50,000 gates.
Major PLD Manufacturers
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Three big names in this field are
 Xylinx, with 51% of market share
 Altera, with 34%
 Lattice, with less than 10%
Market share numbers retrieved from
Wikipedia on 10/26/2011.
Some Product Lines from Altera and
Xylinx
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Altera
 CPLDs: MAX
 FPGAs: Cyclone, Arria, Stratix
 Programming software: Quartus II
Xylinx:
 CPLDs: CoolRunner, XC9500
 FPGAs: Vertix, Spartan, Kintex, Artix
 Programming software: ISE
PALs and GALs
All PLDs contain arrays. Two important kinds of SPLD are
PALs (Programmable Array Logic) and GALs (Generic
Array Logic). A typical array consists of a matrix of
conductors connected in rows and columns to AND gates.
PALs have a one-time
programmable (OTP)
array, in which fuses are
permanently blown,
creating the product
terms in an AND array.
A
A
B
B
X
Simplified AND-OR array
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
PALs
PALs are programmed with a specialized programmer that
blows selected internal fuse links. After blowing the fuses,
the array represents the Boolean logic expression for the
desired circuit.
A
A
B
B
X
What function is
represented by the array?
X = AB + AB
The function represents an XOR gate.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
GALs
The GAL (Generic Array Logic) is similar to a PAL but can
be reprogrammed. For this reason, they are useful for new
product development (prototyping) and for training purposes.
A
A
B
B
GALs were developed by
Lattice Semiconductor.
X
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
PALs and GALs
PALs and GALs are often represented by simplified
diagrams in which a single line represents multiple gate
inputs. The logic shown is for the XOR gate, given
previously.
Input buffer
A
A
B
B
Single line with slash
indicating multiple AND
gate inputs
Fuse blown
X
X
2
AB
AB + AB
Fuse intact
X
X 2
AB
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
PALs and GALs
The AND-gate arrays in PALs and GALs connected to
macrocells. A macrocell is an OR gate together with
associated output logic. Two types of PAL/GAL macrocells
are shown. For these particular macrocells, the I/O pin can
serve as an input or an output.
Tristate control
From
AND
array
To AND
array
I/O
From
AND
array
I/O
To AND
array
Programmable fuse link to
control output polarity
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
GAL22V10
The GAL22V10 is a typical
SPLD. It has 12 dedicated
inputs pins and 10 pins that
can be used as inputs or
outputs.
Link to datasheet
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
CPLDs
A complex programmable logic device (CPLD) has multiple logic array
blocks (LABs), each roughly equivalent to an SPLD. LABs are
connected via a programmable interconnect array (PIA). Various
CPLDs have different structures for these elements.
The PIA is the interconnection
between the LABs.
I/O
Logic array
block (LAB)
Logic array
block (LAB)
SPLD
SPLD
I/O
PIA
I/O
I/O
Floyd, Digital Fundamentals, 10th ed
Logic array
block (LAB)
Logic array
block (LAB)
SPLD
SPLD
Logic array
block (LAB)
Logic array
block (LAB)
SPLD
SPLD
I/O
I/O
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
CPLDs
The architecture of a CPLD is the way in which the internal elements
are configured. A portion of the Altera MAX 7000 series is shown.
This structure is typical for CPLDs, but densities and features
(macrocells, etc) will vary between manufacturers.
General-purpose inputs
I/O pins
I/O
control
block
Logic array block
(LAB A)
Logic array block
(LAB B)
PIA
Macrocell 1
8Ð16
Macrocell 2
I/O pins
Macrocell 1
36
36
16
16
Macrocell 16
Macrocell 2
8-16
Macrocell 16
8-16
Floyd, Digital Fundamentals, 10th ed
I/O
control
block
8-16
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
CPLDs
Macrocells in the Altera MAX 7000 series can generate up to five
product terms. For expressions requiring more terms, the output can be
expanded as described in the text.
Parallel expanders
from other
macrocells
Product-term
selection
matrix
To I/O
control
block
Associated
logic
Expander example
Shared
expander
36 lines from PIA
15 expander
product terms
from other
macrocells
Floyd, Digital Fundamentals, 10th ed
A
B
C
E +F
ABC(E + F)=ABCE + ABCF
EF
Product term from another
macrocell in same LAB
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
CPLD Macrocells
In addition to combinational logic, many macrocells have
registered outputs available (using programmable flipflops). This allows the CPLD to perform sequential logic.
Parallel expanders
from other
macrocells
Global Global
clear clock
MUX 5
From
I/O
To I/O
MUX 1
Productterm
selection
matrix
PRE
D/T Q
C
MUX 2
VCC
EN
CLR
MUX 3
Shared
expander
MUX 4
36 lines
from PIA
15 expander product
terms from other
macrocells
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Figure 11.24 Commonly used symbol for a multiplexer. It can have any number of inputs.
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 11.25 A macrocell in the Altera MAX 7000 family of CPLDs.
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 11.26 A macrocell configured for generation of an SOP logic function. Red indicates data path.
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 11.27 A macrocell configured for generation of a registered logic function. Red indicates data path.
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Programmable Logic Software
All manufacturers of programmable logic provide software
to support their products. The process is illustrated in the
flowchart.
The first step is to enter
the logic design into
a computer. It is done
in one of two ways:
1) Schematic entry
2) Hardware description
language (HDL).
Design entry
Schematic
HDL
Synthesis
Timing
simulation
Functional
simulation
Implementation
Device
programming
(downloading)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Programmable Logic Software
Design entry
Schematic
HDL
In schematic entry, the design is drawn on a computer screen by
placing components and connecting then with simulated wires. After
drawing the schematic, it can be reduced to a single block symbol:
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Functional Simulation
Functional
simulation
After entering the circuit, the circuit is tested in a
functional simulation. You can test the circuit with
waveforms to verify the operation.
The following shows the functional test of a counter
using a waveform editor:
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Synthesis
Synthesis
After the simulation, the computer program optimizes
the logic by eliminating redundant terms and generating
a netlist, (a connection list) that is a complete
description of the circuit.
net1
net2
and1
net3
Netlist
net5
net4
net6
and2 net10
net7
net9 net8
inv1
I1
net14
A0
net11
net12 and3 net15
net13
inv2
I2
net17
A1
inv3
I3
net16
net18 and4
net20
net19
net23
A2
inv4
I4
A3
Floyd, Digital Fundamentals, 10th ed
net21
net22 and5 net25
net24
O1
or1
net26
Z
Netlist (Logic3)
net<name>: instance<name>, <from>; <to>;
instances: and1, and2, and3, and4, and5, or1, inv2,
inv3, inv4;
Input/outputs: I1, I2, I3, I4, O1;
net1: and1, inport1; I1;
net2: and1, inport2; I2;
net3: and1, inport3; I3;
net4: and1, inport4; I4;
net5: and1, outport1; or1, inport1;
net6: and2, inport1; I1;
net7: and2, inport2; I3;
net8: and2, inport3; inv2,outport1
net9: and2, inport4; inv4,outport1
net10: and2, outport1; or1,inport2;
net11: and3, inport1; inv2,outport1
net12: and3, inport2; inv3,outport1
net13: and3, inport3; I4;
net14: and3, inport4; I1;
5: and3
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Implementation
Implementation
The computer next “maps” the design from the netlist to
fit it to a target device. Data for all potential target
devices are in a software library. The computer must
account for the I/O pins and fit the logic to the target
device.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Timing Simulation
Timing
simulation
After implementation, a timing simulation is done that
takes into account the specific delays in the target device
and verifies that there are no problems with the timing. As
in the case of the functional simulation, the waveform
editor can be used to review final timing.
Waveform Editor
If a problem is revealed, it is
not too late to correct it
before downloading the file.
1 ms
Name:
8 ms
12 ms
16 ms
A0 0
A1 0
A2 0
A3 0
Z
Floyd, Digital Fundamentals, 10th ed
4 ms
Glitch
X
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Device Programming
Device
programming
(downloading)
The final step is to send the programming file from the
computer to the target device and test the implementation.
Shown is a PLDT-2
prototyping board with an
Altera PLD as the target
device. Connections are added
to the board from a pulse
generator and oscilloscope to
test the actual circuit in a
laboratory environment. The
prototyping board has built-in
power supplies, interfacing,
I/O, and more.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms
PAL A type of one-time programmable SPLD that consists
of a programmable array of AND gates that connects
to a fixed array of OR gates.
GAL A reprogrammable type of SPLD that that is similar
to a PAL except it uses a reprogrammable process
technology, such as EEPROM instead of fuses.
Macrocell Part of a PAL, GAL, or CPLD that generally consists
of one OR gate and some associated output logic.
CPLD A complex reprogrammable logic device that consists
basically of multiple SPLD arrays with programmable
interconnections.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved