Transcript Slide 1
RobOps - Arithmetic Operators for Future Technologies Carlos Arthur Lang Lisbôa, Luigi Carro, Erika Cota ETS 2005 Future technologies, bellow 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, a different design approach must be taken. Introduction Sample 8-bit Stream Multiplier (RobOp) Who cares about multiple simultaneous transient faults ? Module 1 (faulty) wrong output Module 2 (no fault) Module 3 (faulty) correct output wrong output 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 a b Vdd 7.1 6.1 5.1 4.1 3.1 2.1 1.1 0.1 7.2 6.2 5.2 4.2 3.2 2.2 1.2 0.2 7.3 6.3 5.3 4.3 3.3 2.3 1.3 0.3 V O wrong T output E R 7.4 6.4 5.4 4.4 3.4 2.4 1.4 0.4 7.5 6.5 5.5 4.5 3.5 2.5 1.5 0.5 12 a.b a.b a.b a.b a.b a.b a.b a.b 1 1 1 1 7.6 6.6 5.6 4.6 3.6 2.6 1.6 0.6 7.7 6.7 5.7 4.7 3.7 2.7 1.7 0.7 TMR can not withstand multiple upsets Bit Stream Representation of Products • 64 robust 1-bit multipliers (see detail) generate the 15 “column bit streams” • total of 512 AND gates (64 multipliers x 8 gates) • each column stream is independent from those of the other columns (different weights) • each column stream has 8 to 64 data bits plus 4 bits equal to 1 (see detail) • total of 572 output bits (512 + 15 x 4) • conversion to binary code (counting bits equal to 1 in the stream) postponed Sample 5-tap FIR Filter using RobOps Fig. 1 – Proposed Multiplication Algorithm - bit stream product (the count of 1’s in the stream is equal to the product value) b48 .. b48 b47 .. b47 ... b0 .. b0 1 1 1 1 0 0 0 8 times 8 times 8 times +4 cctr cctr cctr total count of 1’s = 8 * product + 4 number of redundant bits 1 2 3 4 r balance of positive flips 0 1 3 7 2r-1-1 balance of negative flips 1 2 4 8 2r-1 cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr converter Fig. 2 – Adding robustness to the bit stream Table 1. Bit Stream Tolerance to Multiple Upsets cctr • • • • • 5 robust multipliers generate 75 (5 x 15) product column streams each column in the filter shares the same 4 redundant bits (bits = 1) combinational circuits (cctr) count bits equal to 1 in each column stream 2 lsbits of the counters are discarded (pseudo division by 4) converter circuit adds bit counts from each column (according to their weights), thus generating the binary coded filter output • product streams stand up to 3 bit flips in each column • conversion from bit streams to binary code (counters and adders) not yet protected Conclusions Table 2. Redundant Bits x Fault Tolerance f 2 2 2 2 3 3 3 3 4 4 4 4 r 1 2 3 4 1 2 3 4 1 2 3 4 flips + balance flips balance 0 1 3 7 0 1 3 7 0 1 3 7 1 2 4 8 1 2 4 8 1 2 4 8 Notes: • “r” may be an odd number • fault tolerance does not depend on the factors’ width (f); it depends on “r” • the total quantity of bits that can change to 1 (w/o matching complementary flips) is 2r-1-1 • the total quantity of bits that can change to 0 (w/o matching complementary flips) is 2r-1 Multiplier’s tolerance to multiple simultaneous faults (up to 3 bit flips) already confirmed by experiments When compared with TMR, proposed solution is faster and area is not an issue Future Work Counters and converter must be made tolerant to the same amount of multiple simultaneous faults Implementation and test of the digital filter with the operators Universidade Federal do Rio Grande do Sul - UFRGS Pós-Graduação em Ciência da Computação Grupo de Microeletrônica (GME) Laboratório de Sistemas Embarcados (LSE) http://www.inf.ufrgs.br/gme, http://www.inf.ufrgs.br/~lse Porto Alegre - RS BRAZIL Phone +55 51 33166155 e-mail [email protected] [email protected] erika@ @inf.ufrgs.br