Transcript Roadmap for microelectronics technologies

Radiation tolerance of commercial
130nm CMOS technologies for
High Energy Physics Experiments
Federico Faccio
for the CERN(PH/MIC)-DACEL* collaboration
1
*
DACEL is an INFN project involving the INFN sections of Bari, Bergamo, Bologna, Firenze, Padova, Pavia and Torino
Outline
 Past, present and future:


250nm CMOS with HBD approach for the LHC
experiments
Motivation for moving to 130nm CMOS
 Irradiation results (TID) for 3 different
manufacturers (Foundries)
 SEE results
 Conclusion
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Perugia, 17-20 May 2006
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TID effects in CMOS technologies (1)
Parasitic
MOS
Parasitic
channel
Field
oxide
2. Effects in the
thick lateral
isolation oxide (STI)
between source and
drain of a transistor
Bird’s
beak
1. Effects in the thin gate oxide
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TID effects in CMOS technologies (2)
3. Effects in the isolation oxide (STI), in
between n-well or diffusions
Metal 1
N+ diffusion
STI OXIDE
STI + + + + + + +
N+ diffusion
SUBSTRATE
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Past and present: 250nm CMOS
Hardness By Design (HBD) approach has been used: ELT transistors
G
1.E-01
1.E-02
1.E-03
1.E-04
After 13 Mrad
D
S
Log(Id) [A]
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
Prerad
1.E-10
1.E-11
1.E-12
1.E-13
-0.5
0.0
0.5
1.0
Vg [V]
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1.5
2.0
2.5
Past and present: 250nm CMOS
Hardness By Design (HBD) approach has been used: guardrings
V
V
DD
N+ DRAIN
OXIDE
+ + + + ++
V
SS
P+ GUARD
++
SUBSTRATE
p+ guardring
G
D
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S
F.Faccio
+ + +
+
SS
N+ SOURCE
HEP Foundry Service in 250nm CMOS
 MPW service
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Production summary
900
16
800
N of wafers produced
14
700
N of projects in production
12
600
10
500
8
400
6
300
4
200
100
2
0
0
Y 1999
Y 2000
F.Faccio
Y 2001
Y 2002
Y 2003
Y 2004
Y 2005
7
N of projects in production
N of wafers produced
organized for
more than 100
different ASICs
 More than 20
different designs
in production
(some are multiASIC)
 More than 2000
wafers (8-inch)
produced!
Motivation to move to 130nm
 LHC upgrades & SLHC will require higher-
performance ICs, tolerant to larger TID levels
 250nm is already an old process and will not
stay around much longer
 More-modern CMOS processes have the
potential of higher TID tolerance and much
better performance
 What is the radiation tolerance? HBD
needed?
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Outline
 Past, present and future
 Irradiation results (TID) for 3 different
manufacturers (Foundries)





Experimental details
Core transistors, linear layout
Core transistors, ELT
I/O transistors
Need for guardrings…
 SEE results
 Conclusion
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Test structures and measurement setup
 3 commercial 130nm CMOS




processes: foundries A,B and C
Some are PMDs from foundry,
some custom-designed test ICs
NMOS and PMOS transistors,
core and I/O devices (different
oxide thickness), FOXFETs
Testing done at probe station –
no bonding required
Irradiation with X-rays at CERN
up to 100-200Mrad, under worst
case static bias
 Further studies (p source,
reliability, SEGR, noise, …) are
under way
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Core NMOS transistors, linear layout (1)
 Wide transistors (W > 1mm):
 Narrow transistors (W < 0.8mm):
 When the transistor is off or
 An apparent Vth shift (decrease)
for narrow channel transistors
in the weak inversion regime:
 The narrower the transistor, the
 Leakage current appears
larger the Vth shift (RINCE)
(for all transistor sizes)
 Weak inversion curve is
distorted
Foundry A, 2/0.12
Foundry A, 0.16/0.12
1.E-03
1.E-02
1.E-04
1.E-03
1.E-05
1.E-06
1.E-05
1.E-06
Pre-rad
3Mrad
136Mrad
2d HT ann
1.E-07
1.E-08
1.E-09
1.E-10
-0.5
Id (A)
Id (A)
1.E-04
1.E-07
Pre-rad
3Mrad
136Mrad
2d HT ann
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
0.0
0.5
1.0
1.5
2.0
-0.5
Vg (V)
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0.0
0.5
1.0
1.5
2.0
Vg (V)
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Core NMOS transistors, linear layout (2)
 Effect on the leakage current

0.16/0.12
0.32/0.12
0.48/0.12
0.8/0.12
2/0.12
10/1
10/10
ELT
Foundry A
Peak in leakage at a TID of
1-5Mrad
Peaking dependent on dose
rate and temperature,
difficult to estimate in real
environment
1.E-06
1.E-07
Ileak (A)

1.E-05
1.E-08
1.E-09
1.E-10
1.E-11
1.E+05
pre-rad
1.E+06
1.E+07
1.E+08
1.E+09
annealing
TID (rad)
1.E-05
Foundry
C
1.E-06
1.E-06
1.E-07
1.E-07
Ileak (A)
Ileak (A)
1.E-05
Foundry
B
1.E-08
N_10_013
1.E-09
N_10_10
1.E-08
N_10_012
N_088_012
1.E-09
N_04_013
N_053_012
N_024_013
N_018_013
1.E-10
1.E-10
N_028_012
N_014_013
1.E-11
1.E+04
pre-rad
1.E+05
1.E+06
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1.E+07
1.E+08
N_016_012
1.E+09
1.E-11
1.E+04
pre-rad
TID (rd)
F.Faccio
1.E+05
1.E+06
1.E+07
1.E+08
annealing
1.E+09
TID (rd)
12
Core NMOS transistors, linear layout (3)
 Effect on the threshold voltage



Peak in Vth shift at a TID of 15Mrad (A and C)
The narrower the transistor, the
larger the Vth shift (RINCE)
Peaking dependent on dose
rate and temperature, difficult to
estimate in real environment
Foundry B
0.000
-0.020
-0.020
-0.040
-0.040
-0.060
-0.080
-0.120
-0.140
1.E+05
-0.060
N_10_10
-0.080
N_10_012
N_10_013
N_04_013
N_024_013
N_018_013
N_014_013
-0.100
Foundry C
0.000
 Vth (V)
 Vth (V)
Foundry A
N_088_012
-0.100
N_053_012
-0.120
N_028_012
N_016_012
-0.140
1.E+06
1.E+07
1.E+08
1.E+09
1.E+06
1.E+07
1.E+08
1.E+09
TID (rd)
TID (rd)
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1.E+05
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Radiation-induced edge effects - NMOS
E field lines
Polysilicon gate
STI
++ ++
++
Oxide trapped charge
--
--
++ ++
++
STI
Depletion region
Interface states
ID
Main transistor
Lateral parasitic transistor
0
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Core PMOS transistors, linear layout (1)
 No change in the weak
1.E-05
1.E-06
1.E-07
Id (A)
inversion regime, no leakage
 An apparent Vth shift
(decrease) for narrow channel
transistors
 The narrower the
transistor, the larger the
Vth shift
1.E-04
Foundry
A, 0.16/0.12
1.E-08
Pre-rad
3Mrad
30Mrad
136Mrad
1dHT
1.E-09
1.E-10
1.E-11
1.E-12
-0.5
0.0
0.5
1.0
1.5
2.0
Vg (V)
1.E-04
Foundry
C, 0.28/0.12
1.E-05
1.E-05
1.E-06
1.E-06
1.E-07
1.E-07
Id (A)
Id (A)
1.E-04
Foundry
B, 0.14/0.13
1.E-08
Pre-rad
1.E-09
22.5 Mrd
89.5 Mrd
1.E-08
pre-rad
26 Mrd
1.E-09
100 Mrd
1.E-10
1.E-10
1.E-11
1.E-11
1.E-12
1.E-12
-0.5
0.0
0.5
1.0
1.5
-0.5
2.0
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0.0
0.5
1.0
1.5
2.0
Vg (V)
Vg (V)
F.Faccio
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Radiation-induced edge effects - PMOS
E field lines
Polysilicon gate
STI
++ ++
++
Oxide trapped charge
-+
-+
+
+
++ ++
++
STI
Depletion region
Interface states
ID
Main transistor
Lateral parasitic transistor
0
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Core NMOS transistors, enclosed layout (ELT)
Example: Foundry A
NMOS ELT min/0.12
 The radiation
1.00E-04
1.00E-05
1.00E-06
Pre-rad
Id (A)
hardness of the gate
oxide is such that
practically no effect is
observed – verified for
2 foundries (A up to
140Mrad, B up to
30Mrad)
1.00E-03
1.00E-07
3Mrad
1.00E-08
136Mrad
2d HT ann
1.00E-09
1.00E-10
1.00E-11
1.00E-12
-0.2
0.3
0.8
1.3
Vg (V)
PMOS ELT min/012
1.E-03
1.E-04
1.E-05
Id (A)
1.E-06
1.E-07
pre-rad
3 Mrd
40 Mrd
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
-0.2
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0.3
0.8
Vg (V)
1.3
17
I/O transistors, linear layout
1.E-03
Foundry
A, NMOS 0.36/0.24
1.E-04
 Large effect for all sizes,
Id (A)
1.E-06
1.E-07
1.E-08
Pre-rad
1.8Mrad
136Mrad
2d HT ann
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
-0.5
0.5
1.5
2.5
Vg (V)
1.E-02
Foundry
A, PMOS 2/0.24
1.E-03
1.E-04
1.E-05
1.E-06
Id (A)
but more important for
narrow channel transistors
 Results different with
Foundry, but for all
enclosed layout is
required already for TID
levels of the order of 50100krad (NMOS)
 Effect is not negligible
also for ELTs: relevant Vth
shift!
1.E-05
1.E-07
1.E-08
Pre-rad
3Mrad
30Mrad
136Mrad
1dHT
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
-0.5
0.5
1.5
2.5
Vg (V)
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Are guardrings systematically needed? (1)
 FoxFETs are “Field Oxide
1. N+diffusion to N+diffusion
(source/drain of two neighbor
NMOS transistors)
Transistors”
 Good to characterize isolation
properties with TID
 Structures available in only 1
technology (1 only Foundry)
G
D
S
Metal 1
N+ diffusion
STI OXIDE
STI + + + + + + +
N+ diffusion
Foxfet 200/0.18
1.E-03
ann 2 weeks
1.E-04
65 Mrd
1.E-05
25 Mrd
1.E-06
5 Mrd
3 Mrd
1.E-07
Id (A)
SUBSTRATE
pre-rad
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
-10.00
0.00
10.00
20.00
30.00
40.00
Vg (V)
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Are guardrings systematically needed? (2)
2. N+diffusion to Nwell (Nwell with
PMOS logic to drain/source of
NMOS logic)
G
D
S
Metal 1
N+ diffusion
STI OXIDE
STI oxide
+++++
N+ WELL CONTACT
N WELL
SUBSTRATE
Foxfet 200_03
Vg=2.5V
1.E-04
1.E-05
1.E-04
Vg=2.5V
1.E-05
1.E-06
1.E-06
1.E-07
1.E-07
1.E-08
annealing
40 Mrd
6 Mrd
3 Mrd
100 krd
pre-rad
1.E-03
I (A)
Id (A)
Foxfet 200_06
annealing
40 Mrd
6 Mrd
3 Mrd
100 krd
pre-rad
1.E-03
1.E-08
1.E-09
1.E-09
1.E-10
1.E-10
1.E-11
1.E-11
1.E-12
1.E-12
1.E-13
-10.0
1.E-13
-10
10
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30
50
Vg (V)
70
90
10.0
30.0
50.0
70.0
90.0
Vg (V)
F.Faccio
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Are guardrings systematically needed? (3)
Realistic test structure with series of Inverters + DFF along 350um, and
with different separation between n-well (PMOS logic) and NMOS:
Vdd
N-well
Without guardring
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Vdd
Vdd
N-well
Partial guardring
F.Faccio
N-well
Full guardring
21
Are guardrings systematically needed? (4)
1.0E-04
I (A)
1.0E-05
NoGuard
FullGuard
PartialGuard
1.0E-06
1.0E-07
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
TID (rad)
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Outline
 Past, present and future
 Irradiation results (TID) for 3 different
manufacturers (Foundries)
 SEE results
 Conclusion
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SEE results: the SRAM circuit
 16kbit SRAM test circuit designed using the
SRAM generator from a commercial library
provider – not dedicated rad-tolerant design!
 Test performed with Heavy Ions at the
Legnaro National Laboratories accelerator in
June 2005
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Heavy Ion irradiation results
 Test at Vdd=1.5 and

Cross-section 15-30
times larger in LHC
environment
2
1.E-08
1.E-09
Vdd=1.5V
Vdd=1.25V
Weibull
1.E-10
0
5
10
15
20
25
30
35
40
45
50
2
LET (Mev/cm mg)
2
/bit)
1.E-07
Cross-section (cm
1.25 V, results very
similar
 Sensitivity to very low
LET values (threshold
below 1.6 MeV/cm2mg)
 Comparison with
0.25mm memory (rad-tol
design!!):
Cross-section (cm /bit)
1.E-07
1.E-08
0.13um SRAM @ 1.5V
1.E-09
Weibull 0.13SRAM
0.25um SRAM
Weibull 0.25SRAM
1.E-10
0
5
10
15
20
25
30
35
40
45
50
2
LET (MeV/cm mg)
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Challenges for 130nm
 Technology more expensive than ¼ micron:
Strong push for first working silicon
 Strong push for common solutions to similar problems
 Technology more complex than ¼ micron:
 Reduced Vdd, difficult for analog
 Physical effects can not be ignored: proximity effects, filling
requirements, “cheesing”, …
 As a consequence, design rules are considerably more
complex (impressive growth of the design manual)
 Larger number of tools is needed
 Competence in radiation effects are also required
 If non-enclosed transistors are used
 To protect circuits from SEEs
 All competences in technology, design techniques and tools
necessary for a successful project are more difficult to gather in
a group of small size

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Conclusion
 HBD in quarter micron has made LHC electronics
possible/affordable: large scale application of HBD is
a reality!
 Natural radiation tolerance of 130nm better than for
the quarter micron technology (not for I/O
transistors), but Mrad-level still requires HBD for
reliable tolerance
 Large effort required to develop library, acquire tools,
master the technology:

Working with 130nm is MUCH more complex and
expensive; pressure to get quickly to working silicon
 CERN is preparing a frame contract with 1 selected
Foundry, to develop library/design kit/design flow
serving the whole HEP community
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