Transcript Systems In a Package (SIPs) bouwstenen voor de slimme omgeving

Multilayer thin film technology
enabling technology for solving high density
interconnect and assembly problems
Eric Beyne
IMEC, Kapeldreef 75, B-3001 Leuven
IWORID 2002
Amsterdam
September 10, 2002
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Outline
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Introduction :
Impact scaling trends microelectronic circuit
technology on packaging & interconnection
technology
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
Interconnect technology gap

Multilayer thin film technology

Application examples

Conclusion
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Trends in IC process technology
Continuous miniaturization
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Minimum Feature Size (nm)
(DRAM Half-Pitch)
500
350
250
180
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70
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ISMT Litho 2001 Plan
(2-year cycle to 50nm)
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1998 / 1999 ITRS
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2000/2001 ITRS
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System-on-a-chip, SOC
SIA Roadmaps : continuation of Moore’s Law
 Decreasing
transistor size : smaller die for same
function
 For
the same functionality : higher I/O density
 Faster
transistor operation
Increasing system complexity
 Up
to today : faster growth than size reduction
 larger die sizes
 Feasibility
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of “System-on-a-Chip” SOC architectures
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System-in-a-package, SIP
Single Chip SOC systems ?
 There
is a divergence among Si-technologies : high
density logic (CMOS), Memory, Analog, rf, MEMS,….
 Systems consist of many non-silicon components :
Passives, Displays, sensors, antennas, connectors, …
 SOC
 single component system
“System-in-a-Package” SIP solution :
= Multiple components on a high density interconnect
substrate, realizing a (sub)-system function
Contradiction SOC - SIP ?
Because of SOC, (sub)systems may be miniaturised to
the scale of a package
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Miniaturisation of Electronic Systems
Enabling Technologies :
 Si-integration
: SOC
 High
Density Interconnection
technologies
SIP – “System-in-a-package”
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Interconnection technology
Example : Direct chip attach of bare die on printed
circuit board
Chip/board
area ratio
very low
Motorola
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Limited by the
Printed circuit board
technology
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The Interconnection gap
Improvement in density of standard interconnection
and packaging technologies is much slower than the
IC trends
PCB scaling
Advanced PCB
Laser via
Interconnect Gap
IC scaling
Time
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The Interconnection gap
Requires new high density Interconnect technologies
PCB scaling
Advanced PCB
Thin film lithography based
Interconnect technology
IC scaling
Reduced Gap
Time
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The interconnect gap
300
Via Diameter (mm)
Via hole Ø SBU board
Via pad Ø SBU board
250
Via hole Ø thin film
Via pad Ø thin film
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150
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Scaling Most advanced
PCB technologies (SBU)
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0
IC
Technology
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40
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Line Width/Spacing (m m)
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Connecting high density IC’s
PCB
IC
• Peripheral
Bond pitch :
100 40 mm
• High speed
Direct attachment
Wire bond or flip chip
• Laminate
technology
• Line width &
Spacing :
100  50 mm
PCB dimensions
Not compatible with
Ultra fine-pitch flip chip
or wire bonding
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Connecting high density IC’s
IC
• Peripheral
Bond pitch :
100 40 mm
• High speed
Chip sized package
• Area array redistribution
(multilayer thin film)
• “above” IC processing
• Solder ball connections, 300 mm Ø
• Solder ball pitch : 800 300 mm
PCB
• Laminate
technology
• Max.contact
pitch :
800500 mm
Only for large area die
(low I/O density)
Such as memory
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Connecting high density IC’s
PCB
IC
• Peripheral
Bond pitch :
100 40 mm
• High speed
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“Interposer”
• Laminate
technology
• Max.contact
pitch :
800500 mm
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Function IC package :
“Geometry transformer”
The fine I/O pitch has to be connected to the coarser
interconnect pitches on board level
IC
Package – “Interposer”
Interconnect
Board
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Connecting high density IC’s
Wire bonding
IC
• Peripheral
Bond pitch :
100 40 mm
• High speed
PCB
• Down to 40 mm pitch
“Interposer”
• High density
substrate
Flip Chip
• Laminate
technology
• Max.contact
pitch :
800500 mm
• Peripheral
Down to 40 mm pitch
• Area array redistribution
Below 250 mm pitch
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Connecting high density IC’s
Multiple IC
Wire bonding
IC
• Peripheral
Bond pitch :
100 40 mm
• High speed
• Down to 40 mm pitch
“System-In“Interposer”
a-Package”
• High density
substrate
Flip Chip
Multilayer thin film
SIP
• Peripheral
Down to 40 mm pitch
• Area array redistribution
Below 250 mm pitch
PCB
• Laminate
technology
• Max.contact
pitch :
800500 mm
Technology with
embedded passives
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Passives
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Thin film metal interconnect patterning
Lift-off metal patterning
Deposition lift-off
photoresist
Photoresist
Metal deposition
patterning (shape!)
(evaporation)
Lift-off resist :
gap  pattern
Subtractive etching
Deposition with
uniform
thickness
Resist deposition
& photo patterning
Wet etch
(isotropic)
Resist strip :
gap >> pattern
Semi-Additive electroplating
Resist deposition &
photo patterning Electrodeposition
on metal seed layer
(Thick) Metal
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Resist strip
Seed layer
back-etch :
Gap  pattern
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Thin film metal interconnect patterning
Subtractive technique : e.g. Ti/Cu/Ti layers
Advantages :
 smooth metal surface
 excellent thickness control
 low number of process steps
 Mulilayer metal stacks easy
Disadvantages :
 limited thickness of metal layers
 precision limited by wet etching
min. space/width : 15mm / 10mm
 High capital cost of equipment
and materials
Semi-additive : e.g. Ti/Cu seed layer + Cu plating
Advantages :
 thick metal layers possible
 definition by photoresist :
lines up to 10 mm thick,
min. line width / spacing :
down to 5mm/5mm
 Lower cost process
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Disadvantages :
 difficult thickness control
 relatively rough surfaces
 many processing steps involved
 only limited number of metals
available (Cu, Ni, Au, Ag, Co,…)
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Key features
multilayer thin film technology

Metal interconnect lines
 Dimensions
:
• Width/Spacing : 20/10 mm down to 5/5 mm
• Thickness : 1 mm up to 5 mm
 Copper : additive electroplating
 Metal finish : Ni/Au plating

Dielectrictric layers
polymers – e.g. BCB
 Thickness per layer : 5/10 mm
 Via hole diameter : 20 – 40 mm
 Spin-on

Integrated passives
 Thin
film resistors (TaN, NiCr,…)
 Thin film capacitors (Ta2O5, SiN4,…)
 Inductors : Cu
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Wafer Level Pad Redistribution
for flip chip and wafer level CSP
Flip chip redistribution
Solder balls <100 mm
Wafer level CSP
Solder balls >300 mm
S i w a fe r
B C B D ie le c tric
Si wafer
Dielectric (BCB)
C u /lo w K in te rc o n n e c t
E le c tro p la te d C u
Cu/low K interconnect
Electroplated Cu
C u b o n d pa d
E le c tro p la te d N i (U B M )
Cu bond pad
Electroplated Ni (UBM)
C h ip pa s s iv a tio n
E le c tro p la te d s o ld e r b u m p
Chip passivation
Electroplated Au
Preform solder ball
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Thin film Interposer technology
Thin film Redistribution process
on on laminate substrate
60 mm flip chip bump pitch
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High Density Thin Film Interconnects
for Digital Applications
Technology :
Substrates : 150 mm Ø, Si, glass,
ceramic, high Tg laminate or metal.
 BCB spin-on photosensitive dielectric
layers
 Cu lines, 3-5mm thick, down to 10mm
wide lines & spaces
 Metal finish top surface : Cu/Ni/Au
 Power & ground layers : 2 mm thick Al
 Integrated decoupling
capacitors (0.75 nF/mm2)

Design :
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“Manhattan” style X-Y
routing,
Automated design
methodology
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Thin Film Digital Multi-chip Modules
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Current Electronic systems
Philips
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High component count & Large variety of technologies
Majority of components : passives
Many
non-silicon components : displays, key-pad, connectors … 24
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Multilayer Thin Film with Integrated
Passives for rf Front-end circuits
Features :
 Coplanar
lines
 Electroplated Cu lines (3-5 mm thick)
 Resistors : TaN (25 /)
: Ta2O5 (0.72 nF/mm2) &
BCB (5 pF/ mm2)
 Inductors : up to 50 nH, Q : 30 - 150
 Flip chip IC interconnections
 Capacitors
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Multilayer thin film with integrated passives
Design library
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Multilayer thin film with integrated passives
Circuit implementations examples
Blue-tooth
Rf circuit
Integrated Passive device
Multiband cell phone Amplifier
RF section
WLAN receiver - 5.2 GHz
Sub-harmonic
QPSK modulator
LO @ 7 GHz,
RF @ 14 GHz
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Conclusion

Interconnect technology scales much slower than
integrated circuit technology, creating an
“Interconnect Gap”.

Multilayer thin film
 can
bridge the interconnect Gap
 Key
technology for flip chip and on-chip pad
redistribution
 Can
be used for building high density interposer
substrates
 is
an enabling technology for true “Systems In a
Package” (SIPs)
 Enables
 Offers
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integration of high quality passive components
excellent high frequency performance
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Questions ?
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