Transcript CERN_June_2006_final

Silicon-on-Sapphire (SOS) Technology
and the Link-on-Chip Design for LAr
Front-end Readout
Ping Gui, Jingbo Ye, Ryszard Stroynowski
Department of Electrical Engineering
Physics Department
Southern Methodist University
ATLAS Liquid Argon Colorimeter Upgrade Workshop
June 23, 2006
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Outline
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
Introduction
Silicon-on-Sapphire (SoS)
Technology
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SoS Test Chip
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Link-on-Chip Design
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Radiation-hardening-by-Design (RHBD)
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The wide availability of commercial IC processes has led
to the philosophy of “radiation hardening by design”.
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Explore circuit topologies and layout techniques to create
radiation-tolerant circuits
• Submicron bulk CMOS
 inexpensive
• BiCMOS
 ideal for mixed-signal design, but very expensive
• SOI/SOS
 relatively new, growing in popularity
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Radiation Hardening by Design
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Total Dose Effect
• Enclosed layout Transistors
• Guarded ring
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Single Event Effect
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G. Anelli, 2000 IEEE Nuclear Science Symposium and
Medical Imaging Conference
Marjory vote circuits
Error detection/correction Coding
Charge dissipation technique
Temporal filtering technique
Trade-off between radiation tolerance,
performance, area and power dissipation.
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Radiation-hard design challenges
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Techniques that minimize one radiation
mechanism may have little or no effect on
another.
Years ago, total dose concerns dominated
radiation tolerant design, but they are now
secondary to single event effects (SEEs).
SEEs have grown in importance as feature sizes,
capacitances, and operating voltages have been
reduced.
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IC Feature Size and Radiation Effects
Tim Holman, Radiation Effects on Microelectronics Short Course 2001
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Peregrine’s SOS Technology
•No Single-event Latch-up
in SoS CMOS!
BULK CMOS
SOS Process
P channel FET
•Increased immunity to
SEE
N channel FET
sio2
100 nm
Insulating sapphire substrate
Peregrine’s SOS
200 mm
industry’s first and only commercially qualified
SOS technology
•Ideal for radiationtolerant mixed-signal
circuit design due to
minimum substrate noise
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Process Features

Minimum substrate noise
• Higher level integration of RF,
mixed-signal and digital
circuitry.
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Reduced Parasitic capacitance
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High performance
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Low Power consumption
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Minimum crosstalk
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Widely used in RF and space
products
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Transparent substrate allows for
compact and simple integration
with optical devices
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Flipped OE devices on SoS substrate
UTSi
integrated
photo
detector
UTSi integrated circuitry
VCSEL driver circuitry
quad VCSEL array
flip chip
attachment
receiver circuitry
quad PIN array
200 um
transparent
sapphire
substrate
(UTSi)
active
CMOS
layer
MMF ribbon fiber
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Flip-chip bonding of OE devices to CMOS on sapphire
• No wire-bonds – package performance scales to higher data rates
• Rugged and compact package
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Peregrine Space Optical Transceiver
MTP Connector Module
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0.5-um SoS
Single 4+4 transceiver component
with variable data rates (CML
interface)
• Minimum data rate – 10 Mbps
• Maximum data rate – 2.7 Gbps per
channel
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Radiation
• Total Ionizing Dose: 100 kRad(Si)
• SEU: > 20 MeV-cm2/mg
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15 mm height
Berg MegArray PCB socket
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15 year operational lifetime
125 mW per channel power
consumption (dissipated to panel
mount)
Vibration
• 15.33 gRMS for 3 minutes total
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SoS CMOS v.s. Bulk CMOS
0.25 mm SoS
0.13 mm Bulk CMOS
Performance
Up to 10 GHz
Up to 10 GHz
Leakage
Current
Substrate as an insulator
(1014 ohm/m at room
High Leakage current
Power
Dissipation
Reduced parasitic capacitance
also leads to a lower power
dissipation
Crosstalk
Minimum crosstalk due to
reduced substrate capacitance
Substrate noise causes
crosstalk between
channels
Cost
$100k for wafer mask set;
$1000 per wafer
$800k for wafer mask
set; $800 per wafer
temperature). Reduced
substrate junction capacitance
leads to lower leakage
current.
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Back-channel Leakage Current in SOS
Possible Leakage path along the Si/Sapphire interface
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Preliminary Radiation Test Results on
0.5-µm SoS CMOS Technology
2.5Gbps
Before
radiation
Transceiver chip made in
0.5um SoS CMOS Technology
2.5Gbps
Post-rad
100Mrad
1.6 Gbps
Post-rad
100Mrad
Radiation test setup at the
Northeast Proton Therapy Center
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Dedicated Radiation Test Chip for a
0.25-µm SOS CMOS
• Single NMOS and PMOS
• Ring Oscillators
Current mirrors/
resistors
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Ring oscillators,
Ring oscillators
Shift registers
Transistor
XY matrix
• Shift registers to
characterize SEE
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Shift registers
Individual
Standard Cells
to characterize the
performance and power
dissipation
Standard layout, edgeless
layout, majority vote
circuit, resistively hardened
cells
• Digital Standard cells
• Current mirrors
• Resistors
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Transistor Test Structures
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NMOS and PMOS Array
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PMOS and NMOS with different size
• Different lengths to characterize back-channel leakage
current
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Each transistor implemented in four layouts
• Standard, edgeless (ELT), two-finger and four-finger layout
to characterize edge leakage current
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Edgeless (ELT)
One-finger
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Two-finger
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SOS Rad-hard Test Chip Layout
Majority vote
circuitry
CMOS Ring
Oscillators
Differential
Ring
Oscillator
Shift
Registers
Individual
gates
Resistors
Transistors
array
PLL cells
Chip was submitted for fabrication in Oct. 2005
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Link-on-Chip Architecture
REFclock
encoder
Parallel
Data
Flip-chip
bonding
PLL and
clock generator
serializer
Laser
Driver
Laser
TX
transmitter Module
Optical
data
Receiver Module
Parallel Data
Decoder
REFclock
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Flip-chip
bonding
Photonic
Deserializer
TIA/LA
PIN
Clock/Data
recovery
Improve performance
• No off-chip high speed lines
• Flip-chip bonding reduces capacitance and inductance
Reduce power consumption
• No 50-Ohm transmission lines between chips
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2.5-Gbps Serializer Architecture
5 bit
(1,5,9,13,17)
Bits 1,3,5,7,9,
11,13,15,17,19
SR1
(3,7,11,15,19) Mux1
5 bit
20bit
20-bit
Word
Latch
SR2
Latch
Mux3
5 bit
SR3
Ref_clk
(2,6,10,14,18)
(4,8,12,16,20) Mux2
5 bit
SR4
Load clk
(125MHz)
Latch
Latch
Bits 2,4,6,8,10,
12,14,16,18,20
Shift registers
Word clock
(125MHz)
Serial
output
Half bit clk
(625MHz)
PLL &
Clk generator
Bit clk
(1.25GHz)
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PLL and Clock Generator
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Phase-Locked Loop

Self-biasing structure [1]
• Remove process technology and environmental
variability, low input tracking jitter, Wide
operating frequency range
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Phase-frequency detector
• with equal short duration output pulses for inphase inputs
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Charge-pump with symmetric load
VCO with differential buffer delay stage with
symmetric loads
Loop filter
[1] J. G. Maneatis, “low-Jitter Process-Independent DLL and PLL Based on SelfBiased Techniques”, IEEE JSCC, Vol. 31, No. 11, Nov. 1996.
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PLL Layout
Vcntrl1
gnd
vdd
PFD
S2D
Charge
Pump1
Charge
Pump2
d
i
v
5
Vcntrl2
start
up
div4
D2S
VCO
Bias Gen
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Serializer Layout
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Serializer + PLL & Clock Generator
Serializer
Clk generator
PLL
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1.25GHz PLL Simulation Results
Lock time=1.5us
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Clock Generator Output @ 1.25GHz
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Serializer Simulation at 2.5-Gbps
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Clock generator simulation
@ 1.6GHz
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Serializer Simulation
@ 3.2Gpbs
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Conclusion
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Dedicated test Chip lab has been tested and
fabricated
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Lab and radiation testing is in progress
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Link-on-Chip serializer and PLL & clock
generator components are completed.
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Acknowledgement


Paulo Moreira at CERN-EP/MIC for
sharing GOL link design and many
useful discussions
Peregrine for sharing the cost of the
chip fabrication
Thank You!
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