Transcript Slides - Agenda INFN

SuperB SVT Layer0:
plans on MAPS
and pixels
with Vertical Integration
Valerio Re
INFN Pavia and University of Bergamo
SuperB Workshop
Paris, February 15 – 18, 2009
V. Re
SuperB Workshop, Paris, February 16, 2009
1
Layer 0 Options
• The BaBar SVT technology is adequate
for R > 3cm: use design similar to BaBar SVT
• Layer0 is subject to large background and needs
to be extremely thin: > 5 MHz/cm2, < 0.5%X0
Striplets option: mature technology, not so robust
against background.
• Marginal with background rate higher than
~ 5 MHz/cm2
• Moderate R&D needed on module
interconnection/mechanics/FE chip (FSSR2)
CMOS MAPS option
• new & challenging technology:
• can provide the required thickness
• existing devices are too slow
• Extensive R&D ongoing (SLIM5-Collaboration) on
3-well devices 50x50um2
Hybrid Pixel Option: present detectors tend to be too
thick.
• An example: Alice hybrid pixel module ~ 1% X0
• Possible material reduction with the latest
technology improvements
• Viable option for TDR
V. Re
SuperB Workshop, Paris, February 16, 2009
SHAPER
PREAMPL
DISC
LATCH
2
Deep N-Well (DNW) sensor concept
New approach in CMOS MAPS design compatible with data
sparsification architecture to improve the readout speed potential
SHAPER
PREAMPL
DISC
LATCH
Classical optimum signal processing chain for capacitive detector can be
implemented at pixel level:
• Charge-to-Voltage conversion done by the charge preamplifier
• The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel
collected charge (the gain does NOT depend on the sensor capacitance), reducing
charge loss to competitive N-wells where PMOSFETs are located
• Fill factor = DNW/total n-well area ~90% in the prototype test structures
V. Re
SuperB Workshop, Paris, February 16, 2009
3
Status of Deep N-Well MAPS
•The first generation of Deep N-Well CMOS MAPS with in-pixel
sparsification and time stamping was successfully tested.
•Sensors with different sparsified readout architectures and pixel pitches
were developed for SuperB (large background, equivalent to a continuous beam
operation) and for ILC (intertrain readout) in INFN programs.
SLIM5
APSEL4D
SDR0
Average
Signal
for MIP
(MPV)
=980e-
90Sr
electrons
S/N=
23
32x128 matrix.
Data Driven, continuously
operating sparsified readout
Beam test Sep. 2008
Noise events
V. Re
Cluster signal (mV)
16x16 matrix, Intertrain sparsified readout
25x25 um pitch
50x50 um pitch
SuperB Workshop, Paris, February 16, 2009
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The way forward
•
Next generation of DNW MAPS has to provide devices that approach
actual experiment specifications more closely
•
Several issues have to be addressed to meet SuperB SVT requirements
(pixel pitch, detection efficiency):
–
Binary readout: SVT demands a pixel pitch < 50 mm to achieve
required hit resolution < 15 mm.
Detection efficiency does not meet requirements (~ 99 %) because
of competitive n-wells (PMOS) decreasing the fill factor
Readout architecture has to be scaled to a larger matrix size,
digital-to-analog interferences should be avoided
–
–
•
Two different ways to approach this goal:
1)
A gradual performance improvement
 better sensor layout, optimize interconnections and pixel cell
(remove shaper from APSEL to make room for macropixel lines
and to scale to larger dimensions)  SuperB Layer0 test module
2)
A technology leap
 Vertical integration
V. Re
SuperB Workshop, Paris, February 16, 2009
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APSEL5D for a Layer0 module
demonstrator
• Small size prototype module with functionalities and
cooling/mechanics close to SuperB specifications
• New 128x128 (or 320x80) MAPS chip (APSEL5D)
– 40 mm2 active area, 40mm x 40mm pixel cells
– With respect to APSEL4D, scaling to larger matrix size dictates
to remove the shaper stage to make room for additional
macropixel private lines
– This also makes it possible to reduce the pixel pitch
– Inside the pixel cell, sensor layout has to be changed to increase
detection efficiency (→ 99%)
– A small test chip (APSEL5T) was submitted in January to test
pixel cell changes
– Optimization of readout architecture strategy is needed for the
final chip
– Submission of the large matrix APSEL5D in late 2009 in the
130nm CMOS STMicroelectronics technology
V. Re
SuperB Workshop, Paris, February 16, 2009
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APSEL4D  APSEL5D: analog cell
APSEL4D
APSEL5D
Vf
Discriminator
-
Gm
CF
+
+
Vth
CD
CF
Vth
-
Shaper
Preamplifier
-
Discriminator
–
Pixel cell: 50x50 mm2
–
Sensor capacitance: 400 fF
–
Power dissipation: 30 mW
–
ENC = 60 e rms, threshold
dispersion = 60 e (measurements)
V. Re
CD
C2
Sensing diode
(Deep N-Well)
Sensing diode
(Deep N-Well)
-
iF
–
–
–
–
Pixel cell: 40x40 mm2
Sensor capacitance: 270 fF
Power dissipation: 20 mW
ENC = 30 e rms, threshold
dispersion =25 e (simulations)
SuperB Workshop, Paris, February 16, 2009
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APSEL5T: sensor layout
• Beam test results of APSEL4D show a ~90% efficiency, which
agrees very well with TCAD simulations
• Optimized cell with satellite N-wells surrounding PMOS
competitive N-wells in APSEL5T  Efficiency ~ 99%
• Metal shielding between analog and digital voltages was improved
and made compatible with a large matrix
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SuperB Workshop, Paris, February 16, 2009
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Vertical integration technologies
•
•
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•
A 3D chip is generally referred to as a
chip comprised of 2 or more layers of
active semiconductor devices that
have been thinned, bonded and
interconnected to form a “monolithic”
circuit.
Often the layers (sometimes called
tiers) are fabricated in different
processes.
Industry is moving toward 3D to
improve circuit performance.
– Reduce R, L, C for higher speed
– Reduce chip I/O pads
– Provide increased functionality
– Reduce interconnect power and
crosstalk
This is a major direction for the
semiconductor industry.
V. Re
Optical In
Opto Electronics
and/or Voltage Regulation
Power In
Optical Out
Digital Layer
Analog Layer
50 um
Sensor Layer
Physicist’s Dream
Pixel control, CDS,
A/D conversion
Diode
Diode
Analog readout Analog readout
circuitry
circuitry
Diode
Diode
Digital
Analog
Sensor
Analog readout Analog readout
circuitry
circuitry
Conventional MAPS 4 Pixel Layout
SuperB Workshop, Paris, February 16, 2009
3D 4 Pixel Layout
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MAPS and Vertical Integration
• Overcome limitations typically associated to
“conventional” and DNW CMOS MAPS:
– Reduced pixel pitch
– 100 % fill factor (few or no PMOS in the sensor layer)
– Better S/N vs power dissipation performance (smaller sensor
capacitance)
– Reduction of digital-to-analog interferences
– Increased pixel functionalities (removal of layout constraints
allow for an improved readout architecture, analog
information,….)
– Fully-depleted, high-resistivity substrate: larger signal, fast
charge collection, radiation hardness, …..
V. Re
SuperB Workshop, Paris, February 16, 2009
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Pixel Sensors
and Vertical Integration Technologies
•
The very crowded zoo of vertical integration processes can be
reduced to two different basic approaches (and technical problems):
1.
Interconnection between 2 (or more) CMOS layers,
one layer with a MAPS (DNW) device and analog front-end, and the
other layer(s) with the digital readout
2.
Interconnection between a CMOS readout electronics chip (2D or
3D) and a fully-depleted high resistivity sensor
a) with bump bonding (standard, but low pitch may be needed)
b) with a vertical integration technique (low material budget, more
advanced)
–
“Pixel systems for thin charged particle trackers based on
vertical integration technologies” - VIPIX
(INFN Pisa, Pavia, Bologna, Trieste, Trento, Perugia, Roma3,
Torino)
-
Approved and funded INFN program for a 3-year duration
V. Re
SuperB Workshop, Paris, February 16, 2009
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3D vertical integration based on DNW MAPS
(conceptual)
12
Use vertical integration
technology to interconnect two
130nm CMOS layers
Handle for CMOS
Mostly digital CMOS
tier
PMOS
Standard CMOS
NMOS
Tier interconnection and vias
with industrial technique
Analog and sensor
CMOS (mostly NMOS)
tier
V. Re
NMOS
PMOS
P-well
Buried N-type
layer
Deep N-well
structure
Standard N-well
P-substrate
SuperB Workshop, Paris, February 16, 2009
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Tezzaron vertical integration
process flow (VIA FIRST):
• multi-tier tier chip; Tezzaron includes
standard CMOS process by Chartered
Semiconductor, Singapore.
Step 1: Fabricate individual tiers; on
all wafers to be stacked: complete
transistor fabrication, form super
via Fill super via at same time
connections are made to transistors
6 mm
Cu
Wafer-n
Step2: Complete
back end of line
(BEOL) process
by adding Al
metal layers and
top Cu metal
(0.7 mm)
Wafer-n
Wafer-2
Step 3: Bond
wafer-2 to first
wafer-1 Cu-Cu
thermocompression
bond
Wafer-1
Cu-Cu bond
All wafers are bulk
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SuperB Workshop, Paris, February 16, 2009
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Tezzaron vertical integration process flow:
Step 4: Thin the wafer-2 to about 12 um to
expose super via. Add Cu to back of wafer-2
12um
to bond wafer-2 to wafer-3
OR stop stacking now! add metallization on
back of wafer-2 for bump bond or wire bond
Wafer-2
3rd wafer
Metal for
bonding
2nd wafer
Wafer-1
Cu for bonding to wafer-3
1st wafer
V. Re
Step 5: Stack wafer-3, thin wafer-3 (course
and fine fine grind to 20 um and finish with
CMP to expose W filled vias)
Add final passivation and metal for bond
pads
SuperB Workshop, Paris, February 16, 2009
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•
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•
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Advantages
No handle wafers needed
No extra space allotment in BEOL processing for vias
Vias are very small
Vias can be placed close together
Minimal material added with bond process
– 35% coverage with 1.6 um of Cu gives Xo=0.0056%
– No material budget problem associated with wafer bonding.
Good models available for Chartered transistors
Thinned transistors have been characterized
Process supported by commercial tools and vendors
Fast assembly
Via diameter ~ 1.2 um
Lower cost
Pad diameter ~ 1.7 um
Via size plays an
important role in
high density pixel
arrays
2.5 um
V. Re
SuperB Workshop, Paris, February 16, 2009
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3D MPW run
• A 3D multi project run using Tezzaron/Chartered technology is
scheduled at the end of April.
• There will be only 2 layers of electronics fabricated in the
Chartered 130 nm process, using only one set of masks.
• The wafers will be bonded face to face.
• Italian groups will join the run in the frame of a 3D-IC
Consortium between FNAL, IN2P3 and INFN
(http://3dic.fnal.gov)
• The run will include 3D APSEL structures as a first test of a
vertical integration technology for SuperB SVT.
• The run will also include many other chips by French, U.S. and
Italian groups, from MAPS to pixel readout chips (to be bonded
to sensors), from which we’ll learn a lot about vertically
integrated sensors and electronics
V. Re
SuperB Workshop, Paris, February 16, 2009
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High resistivity sensors and
vertical integration
• Much better sensor properties with respect to bulk
CMOS MAPS (larger and faster signal, radiation
hardness,…).
• Material budget (> 1% X0) and pitch of present HEP
hybrid pixel systems is too large for SuperB
• Vertical integration will help reduce pixel pitch and
interconnection material
• A much better S/N vs. power dissipation vs. speed
operating point should be attained with respect to MAPS
• We plan to use pixel detectors (high resistivity, ~ 50 mm
pitch) fabricated by FBK-IRST for studying a system
based on vertical integration technologies associated to
fully depleted sensors
V. Re
SuperB Workshop, Paris, February 16, 2009
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Bump bonding of 3D CMOS Readout Electronics
and high resistivity, fully depleted pixel sensors
• Standard technique for the interconnection between sensor
and electronics; 50 mm x 50 mm bump bonding pitch appears
feasible
• A 3D readout integrated circuit may allow for a small pixel
pitch (50 mm x 50 mm) and at the same time for an improved
readout architecture (for example removing the 4x4
macropixel structure of the APSEL chips).
1st layer
Digital
section
Analog
section
Bump
bondin
g
V. Re
2nd layer
detector layer
SuperB Workshop, Paris, February 16, 2009
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Bump Bonding of small pitch pixels
• Investigate a bump bonding process
compatible with pixelated devices having a
50 micron I/O pitch (technologies are
commercially available).
SnPb (60/40) Bump Bonds
25 mm solder bumps on 50 µm
pitch, fabricated at RTI
V. Re
Cu-Sn Bump Bonds
25 mm Cu-Sn bump bond,
fabricated at RTI
SuperB Workshop, Paris, February 16, 2009
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Readout architecture
and vertical integration
• In APSEL chips, MAPS readout architecture has a
macropixel structure to minimize in-pixel logic (and
PMOS competitive N-wells).
Matrix subdivided in MacroPixel (MP=4x4)
with point to point connection to the
periphery readout logic:
–
Register hit MP & store timestamp
–
Enable MP readout
–
Receive, sparsify, format data to output bus
MP
4x4
pixels
Data lines
in
common
Column
enable
lines in
Periphery readout logic
common
2 MP
private
lines
Data
out
bus
• Vertical integration removes constraints on in-pixel
logic and leads to an architecture without macropixels
and associated private lines.
• Readout architecture can be the same for 3D MAPS
and for high resistivity pixel sensors.
V. Re
SuperB Workshop, Paris, February 16, 2009
20
Vertical Integration of CMOS Readout Electronics
and high resistivity, fully depleted pixel sensors
• Vertical integration may allow for a considerable reduction
of the amount of interconnection material and for a
shrinking of the pixel size (40 mm x 40 mm).
• We plan to verify if the vertical integration process does
not degrade a high resistivity sensor.
• Presently, Ziptronix Direct Bonding Interconnect appears
the most appealing option for low material budget
interconnection.
Digital
section
1st layer
Analog
section
2nd layer
detector layer
V. Re
Wafer bonding and
electrical
interconnection
SuperB Workshop, Paris, February 16, 2009
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Vertical integration between readout chip
and fully depleted sensor: Ziptronix
•
•
•
Some 3D bond processes
introduce significant material
between bonded layers.
– Conventional solder bumps or
CuSn can pose a problem for
low mass fine pitch assemblies
IC bonding to a detector will be
done by Ziptronix using the
Direct Bond Interconnect (DBI)
process.6
– Xo < 0.001%
Tezzaron and Ziptronix have
formed an alliance.
– Good communication between
companies for pad
metallization for sensor
bonding, etc. now exists.
V. Re
•
Ziptronix is located in North
Carolina
•
Orders accepted from
international customers
SuperB Workshop, Paris, February 16, 2009
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Conclusions
• 130 nm 3D Active Pixel Sensors have the
potential for a big performance
breakthrough targeting SuperB
• Advanced microelectronic technologies provide
exciting opportunities for high performance
MAPS and fully depleted pixel sensors
• A lot of work is needed to qualify these
technologies for actual experiments
• Second run with 3D Tezzaron/Chartered
technology and large MAPS matrix and pixel
readout chip foreseen in early 2010
V. Re
SuperB Workshop, Paris, February 16, 2009
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Backup slides
V. Re
SuperB Workshop, Paris, February 16, 2009
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SuperB SVT
• Physics goals set severe requirements:
– High granularity  small pixel pitch
– Low material budget  low mass cooling, thin silicon wafers,
small amount of material for support and interconnections
– Small distance to interaction point  large background
High data rate,
Level 1 trigger
In MAPS, loss of
efficiency due to
in-pixel PMOS
Data sparsification
Full CMOS
V. Re
radiation hardness
(deep submicron
CMOS intrinsically
rad-hard)
Mixed-signal chips
SuperB Workshop, Paris, February 16, 2009
Digital-to-analog
interferences
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Cooling system
• Vertical integration devices lead to an
innovative approach to the cooling
problem:
– Potentially, requirements are more
severe, because vertical integration
may substantially increase power per
unit surface area available for cooling
– Reduction of the impact of the cooling
system on the material budget
• Microchannel cooling
– Conservative solution: microchannels in
sensor mechanical support
– Innovative solution: microchannels in
the silicon wafers with front-end
electronics
(see talk by F. Bosi)
z
~10 um
100 um
Low-Res (electronics)
ball-bonded
50100 High-Res (sensor)
um
V. Re
SuperB Workshop, Paris, February 16, 2009
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Tezzaron Background
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Founded in 2000, located in Naperville, Illinois
Has fabricated a number of 3D chips for commercial customers
Tezzaron uses the “Via First” process
Wafers with “vias first” are made at Chartered Semiconductor in
Singapore.
Wafers are bonded in Singapore
by Tezzaron.
– Facility can handle up to
1000 wafers/month
Bonded wafers are finished
by Tezzaron
– Bond pads
– Bump bond pads
•
Potential Advantages
•
Process is available to customers
from all countries
– Lower cost
– Faster turn around
– One stop shopping!!
V. Re
SuperB Workshop, Paris, February 16, 2009
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Chartered Semiconductor
•
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•
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One of the world’s top dedicated semiconductor
foundries, located in Singapore, offering an
extensive line of CMOS and SOI processes from
0.5 um down to 45 nm.
Offers Common Chartered-IBM platform for
processes at 90 nm and below.
Chartered 0.13 um mixed signal CMOS process
was chosen by Tezzaron for 3D integration
– Chartered has made nearly 1,000,000 eight inch
wafers in the 0.13um process
Extension to 300mm wafers and 45nm TSVs
underway
Chartered 0.13 um process has different layer
arrangement and transistor thresholds than IBM
process.
Commercial tool support for Chartered
Semiconductor
–
–
–
–
DRC – Calibre, Hercules, Diva, Assura
LVS - Calibre, Hercules, Diva, Assura
Simulation – HSPICE. Spectre, ELDO, ADS
Libraries – Synopys, ARM, Virage Logic
V. Re
SuperB Workshop, Paris, February 16, 2009
Chartered Campus
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Chartered 0.13 um Process
• 8 inch wafers
• Large reticule – 24 mm x 32 mm
Eight
• Features
inches
–
–
–
–
–
–
–
Deep N-well
MiM capacitors – 1 fF/um2
Reticule size 24 x 32 mm
Single poly
8 levels of metal
Zero Vt (Native NMOS) available
A variety of transistor options with multiple threshold
voltages can be used simultaneously
•
•
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•
V. Re
Nominal
Low voltage
High performance
Low power
SuperB Workshop, Paris, February 16, 2009
29
Circuit Performance
•
Circuits tested with full substrate
thickness and then after bonding and
thinning to 12 um
– No change in performance between
thinned and bonded devices and
unthinned/unbonded devices.
Wafer before
thinning and
bonding
• Bandgap circuit
• Sense Amplifier
• Charge pump
•
– No change in performance between
thinned and bonded devices before and
after temperature cycling.
Transistor measurements on same
devices before and after thinning and
bonding are shown on the next slide.
– No noticeable difference in
characteristics except small increase in
PMOS speed due to strain in silicon as
expected
Thinned
wafer with
test circuits
bonded to
bottom wafer
Bottom wafer
V. Re
SuperB Workshop, Paris, February 16, 2009
30
Via First Approach
• Through silicon Via formation is done either before or
after CMOS devices (Front End of Line) processing 7
Form vias before transistors
IBM, NEC,
Elpida, OKI,
Tohoku, DALSA….
Tezzaron, Ziptronix
Chartered, TSMC,
RPI, IMEC……..
Form transistors before vias
TWEPP-08
31
Via Last Approach
• Via last approach occurs after wafer fabrication and
either before or after wafer bonding 7
Zycube, IZM,
Infineon, ASET…
Samsung, IBM,
MIT LL, RTI,
RPI….
Notes: Vias take space away from all metal layers. The assembly process
is streamlined if you don’t use a carrier wafer.
TWEPP-08
32
Bonding Choices
Fermilab
experience
Electrical and Mechanical Bonds
1) Bonding between Die/Wafers
a) Adhesive bond
Polymer
(BCB)
b) Oxide bond (SiO2 to SiO2)
c) CuSn Eutectic
Sn
Cu
d) Cu thermocompression
SiO2
bond
Cu3Sn
(eutectic bond)
Cu
bond
Cu
e) DBI (Direct Bond Interconnect)
Metal
(MIT LL)
(RTI)
(Tezzaron)
Oxide
bond (Ziptronix)
Metal bond
For (a) and (b), electrical connections between layers are
formed after bonding. For (c), (d), and (e), the electrical
and mechanical bonds are formed at the same time.
TWEPP-08
33
Thinning and Alignment
• Thinning –
– Thinning is done by a
combination of grinding, CMP
and etching.
– Through wafer vias typically
have an 8 to 1 aspect ratio for
etched vias. Thus, in order to
keep the area associated with
the vias as small as possible,
the wafers should be as thin
as possible.
6 inch wafer thinned to 6 um and
mounted to 3 mil kapton
• Alignment
– Alignment of better than 1 um
(3 sigma) is now possible on
wafer to wafer bonding.
Photos from MIT LL
TWEPP-08
34