Transcript Standard and IO cells (1)

3D Design Flow @ IPHC
Frédéric Morel - Grégory Bertolone Claude Colledani
Standard and IO cells (1)
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Building DfII libraries for ARM cells
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symbols and cmos_sch views: use directly the dfII files
layout view: import of the gds file
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verilog view: import and compile the verilog file
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Use of the metal 5 top for IO cells (for having large VIA4 and no
MET6)
vhdl file is available but not used
schematic view: import of the cdl netlist
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Use a skill function for changing VSS and VDD to VSS! and VDD!
Device mapping between the devices of cdl netlist and Chartered
DfII library (chrt013lp)
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abstract view: import of the lef file
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Change the lef file for metals and vias
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18/03/2010
transistors and resistors, no diode was imported
METALx  METx, VIAxy  VIAx, and VIAxy_H/V  Mx_My
By default layers used in abstract are invisible (LSW)
3D workshops (Marseille)
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Standard and IO cells (2)
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Test of the DfII ARM libraries against CAD tools
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Simulations
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Synthesis, place & route, timing analysis and postsimulations
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tlf files exist to perform timing analysis
RTL compiler, SOC
Post-simulations and post-timing analysis (need handmade
modifications, should be solved)
DRC and LVS
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Analogue (spectre), mixte (ams) and digital (nc-verilog)
These libraries are fully compatible within DfII
Available for others users (NDA signed)
18/03/2010
3D workshops (Marseille)
[email protected]
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Extraction
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Extraction made with Calibre and Hercules/STAR
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Extraction with both tools have similar results
Modification of the original scripts necessary for creating a dspf
extracted netlist
Simulations with spectre and ams in DfII
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Use directly this netlist with a config view
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Import like a cdl netlist for generating a schematic
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Does not work each time (complexity of the extracted cell)
Need to modify the original netlist
 PININFO are not present
 Modifications are handmade but a script can be developed
Need to create a device map file
 For mapping cdl netlist devices and Chartered devices
(Transistors, parasitic and physical resistors and capacitors)
 Once for the kit (not tested with physical resistors and capacitors)
Future plans for a robust extraction flow?
18/03/2010
3D workshops (Marseille)
[email protected]
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Scripts (1)
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MIM capacitances for Calibre LVS
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With 2 top metals options 2 types of MIM cap are available
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For 6 metals layers: METTOP/MET5 and MET5/MET4
Only MIM cap between METTOP/MET5 are extracted
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Modification of the Calibre LVS extract rules
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Extraction of MIM devices between METTOP/MET5
 If 2 top metals options is not set
 Default rules
Extraction of MIM devices between MET5/MET4
 If 2 top metals options is set
 METTOP/MET5 MIM cap are not extracted
Calibre DRC rules take into accounts both types of
MIM cap
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18/03/2010
Are really two types of MIM caps available?
3D workshops (Marseille)
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Scripts (2)
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Verifications of connections between metal 6 BI
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Assura DRC LvL of 2 tiers with specific rules
Check that all BIs are face to face in each tier
Check that BIs with the same label name are face to face in
each tier
Check that BIs which enclose VIATOP are face to face in
each tier
LvL must be done before the mirroring of the second tier
BI
Label1
VIATOP
18/03/2010
3D workshops (Marseille)
Label2
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Scripts (3)
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Array of labels generator
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Arrays of pixels need 1-dim. vectorized
labels
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Pix(x,y) Label<v>
To perform a LVS
To check connectivity between both tiers
This script allows us to create bus labels
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Labels are place as an array
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In Cadence 5.1.41 pin vector limit is set
to 64k in schematic view
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18/03/2010
different size of rows and columns
different horizontal and vertical pitches
Fully customizable
Check and save is very slow
cdl export is also very slow
3D workshops (Marseille)
Lb<1>
Lb<2>
Lb<3>
Lb<4>
Lb<5>
Lb<6>
Lb<11> Lb<7>
Lb<3>
Lb<9>
Lb<1>
[email protected]
Lb<5>
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Scripts (4)
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Check shapes in METx label
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In Calibre METx drawing, dummy and label are extracted as
nets
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In the manufacturing stream layer table METx labels are not
exported
By default the display are the same for all of theses subtypes
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We create a Calibre rules to check if METx labels are used to
create shapes
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Shapes_label.Metalx{@ Shapes in Metal x
COPY Metalx_Label}
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Dummy Filling
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18/03/2010
The filling in this technology is not obvious
We use the CMP filling script (with Assura)
3D workshops (Marseille)
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Miscellaneous (1)
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Stream Layer Map Table
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Some marking layers are defined in marking and drawing
with the same gds subtype
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LVS_PSUB2, SRAMCORE, DIODE_MK, …
Not easy to verify LVS and DRC in the import gds file
Source of mistakes ?
AMS simulations
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18/03/2010
By default models are not load when ams simulator is
chosen
libInitCustomExit.il file must be updated with the right path
Some models files must be also updated (syntax problems)
3D workshops (Marseille)
[email protected]
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Miscellaneous (2)
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Chip ID block
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Placement understanding of the chip ID has been different
from labs to labs
Should we have to clarify this point?
Mailing at IPHC
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For a better diffusion of information we have a new mailing list
[email protected]
People in this list
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18/03/2010
G. Bertolone, G. Claus, C. Colledani, W. Dulinski, Y. Fu, C. Hu,
Morel, O. Torheim, X. Wei and M. Winter
The management of the list is transparent for users
Please use it
3D workshops (Marseille)
[email protected]
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F.
Kit version
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Issues with Chartered/Tezzaron kit versions
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The first kit version has a conflict between Tezzaron and
Chartered
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Both tech file containing identical layer info
Tezzaron rules have changed during the design
DRC with different rules release in IPHC and FNAL
Chartered kit configuration is complex
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There is a lot of options for DRC and LVS
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Options for setting the right process
Options for setting the checks for the DRC
An official procedure for verifying the version of the
rules, the right options set up is necessary
18/03/2010
3D workshops (Marseille)
[email protected]
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Suggestions
Assura
Calibre
Hercules/Star
DRC
Standard process
only
Yes
Yes
LVS
Standard process
only
Yes / MIM cap
modification
Yes / no MIM cap
Extract
Standard process
only
dspf only
dspf only
3D LvL
Yes
Yes / No check of
labels name
No
Filling
Yes
No
No
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How can we have a homogeneous CAD flow?
Same for standard and IO cells?
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With Synthesis, Place and Route, pre- and post- timing analysis
Example of CERN with IBM flow?
18/03/2010
3D workshops (Marseille)
[email protected]
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