Transcript Slides - Agenda INFN

Hybridization,
interconnection advances
Massimo Manghisoni
Università degli Studi di Bergamo
INFN Sezione di Pavia
December 17, 2015
Motivations
 Experiments at the future high luminosity colliders set challenging
requirements on the design of semiconductor pixel detectors
 Designers are currently considering two different approaches:
• moving to higher density 2D technology nodes
• moving to 3D technologies with vertical integration techniques
 3D integration is a technology that makes it possible to devise pixels with
•
•
•
•
advanced architectures
smaller form factor
less material and dead areas
separation of sensing, analog and digital function
 Features of 3D integration can be applied to
• Particle tracking: wide interest in the high energy physics (HEP) community in
view of the design of novel pixel detector systems with advanced readout
electronics
• X-ray imaging: development of advanced X-ray imaging instrumentation for
applications at the free electron laser (FEL) facilities
2 of 25
Outline
Focus of the talk: R&D activity on advanced interconnections
 The AIDA 2020 Collaboration (WP4)
 Pixel modules for tracking at HL-LHC
 High-resolution imagers for photon science application
 Medipix - CERN
 VIPIC - Fermilab
 PixFEL Project - INFN
3
AIDA 2020
WP4 - Task 4.4 Interconnections and TSVs
 CERN, INFN (GE, PV, PG), CNRS (CPPM, LAL)
MPG-MPP, UBONN, UNIGLA
 Coordination: INFN
Bonding and TSV technologies
 Qualification of Industrial bonding techniques: requirements of future HEP
experiments addressed in terms of
 pixel readout cell pitch (order of 20 μm) and geometry
 interconnection density
 Etching TSV in fully processed 65 nm CMOS wafers for peripheral backside
interconnections: the baseline TSV technology will be “via last”
 Explore processes for relatively fine pitch TSVs in thinned CMOS wafers,
which will also include chip backside processing steps
4
LHC Hybrid pixel modules
Flex
FEIx
Sensor
Flex
FEIx
Sensor
5
Wire-bond
Stave surface
Wire-bond
Stave surface
Standard pixel modules
Wire bonds are the weak link
 Oscillation in magnetic field
 Protection required or desired
 Limit on envelopes
 Require flex to be glued very precisely
 Access to bond area on FEIx limits the
sensor active area (not 4-side
buttable)
Modules without wire-bonds
Reverse sensor and FEIx order
 Better controlled envelopes
 Sensor can be larger than FEIx size and
is 4-side buttable
 No fragile wire bonds needed
 Sensor cooled directly by stave
Enabling Technologies
TSV-last + RDL
For Flex to FEIx connection
 Connect chip M1 from front to
back of chip
 RDL distributes all FEIx
connections over full chip surface
• Do not need fine-pitch connections
• Power can be brought to chip at
several places , not just on the edge
Direct laser soldering
for flex to chip connection
 Thin 2-layer Al flex
 No glue layer needed
 Connections are solder 1-by-1,
module stays at RT
 Reworkable
Laser%
Solder%balls%
Flex
Wire-bond
FPC%
Chip%
leti
CEA-LETI
FEIx
6
Sensor
Stave surface
Direct laser soldering
Flex is thin 2-layer Al on Kapton flex with Solder ball (200mm) inside which is
melted by laser
 No module heat up & No thermal stress on module
No glue is needed between flex and bare module
 Solder holds flex mechanically well in place
P. Riedler, A. Di Mauro, A. Junique
(PH-AID ALICE)
Coverlay
Metal
Polyimide
Metal
Coverlay
Chip
27 cm long
7
9 MAPS solder to flex (50 µm thick chips, 15x30mm2 each chip)
7
LETI TSV+RDL
 Medipix & LETI developed TSV on Medipix
IBM chip to allow for BGA assembly for
buttable X-ray/particle detectors
 Second run processed 6 wafers of
Medipix3rx : TSV yield ~ 70% to 80%
M.Campbell /CERN-PH – G.Pares / CEA-LETI
Medipix specifications
Design
Process Flow
8
Wafer view
Test structures
Single chip
Wafer diameter: 200mm
Wafer thickness: ~725um
IC Technology: 130 nm / IBM
Top Surface: Al + Nitride
Chip size : 14100 x 17300 µm
TSV per chip: ~100
TSV aspect ratio :
120:60 µm (MEDIPIX RX)
50: 40 µm (timepix3)
Activity
Collaboration: CERN, Glasgow, LAL & MPI
 Flip chipping at LETI
FEI4 B + Sensor, Satisfactory results (prototype irradiated and Beam tests ..)
 Start With FEI4 , TSV + RDL
 The Future: Build a demonstrator:
TSVs in a 65 nm front-end chip (from RD53 engineering run)
The Ultimate Goal
100 μm
150 μm
or less
back side
TSVs module
front end chip (65 nm)
front side
Bonding …
New (LETI Proprietary)
Bump Bonding
sensor
HV
9
Direct Wafer-to-Wafer bonding
Bond sensor wafer directly to FE wafer
• Remove single die flip-chip process
Cu-Cu / SiO2-SiO2 and hybrid bonding
• Direct bond formed between 2 wafers
bond Cu & Cu / SiO2 & SiO2
• Requires smooth and activated wafer
surfaces (Roughness ~ 0.5 nm)
• Room temperature and room pressure
bond process
Requires
 Post processing at wafer level to
produce smooth surfaces
 Matching wafer size
 Excellent alignment
 TSVs to bring front signal to backside
Wafer-Wafer assembly
Thin ROC wafer is “fused” to
sensor wafer
Allows
 Thin devices (Process as a single
wafer after bonding)
 TSVs to be added after the bond
 Minimizes bond cap/inductance
CEA-LETI Demonstrated direct bonding Cu-Cu, SiO2-SiO2 and more complex Hybrid bonding
10
Bonn/CPPM TSV project
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Goal of the project: develop modules for ATLAS pixel detector at the HL-LHC
using
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3D integration in Photon science
Medipix3 chip





256 X 256 pixels on a pitch of 55μm
130 nm CMOS technology
I/O wire bonding pads compatible with TSV technology
TSV=connections between front and back sides of the ASIC
CERN-LETI collaboration (TSV Last developed by LETI and applied to pixel
detector read- out chip designed and supplied by CERN)
VIPIC1 Demonstrator
 64 X 64 pixels on a pitch of 80 μm
 130 nm CMOS technology
PixFEL Project
 64 X 64 pixels on a pitch of 100 μm
 65 nm CMOS technology
14
VIPIC1 Vertically Integrated Photon Imaging Chip
W2W tier stacking

Cu-DBI (oxide-oxide fusion bonding) used for bonding
tiers of 3D VIPIC
 8” bonded wafer pair with top wafer thinned to expose
6mm TSVs (6mm of silicon left of the top wafer)
D2W ASIC-sensor LTD-bonding

Ni-DBI (oxide-oxide fusion bonding)
15
Detector
 Si d=500 mm, pitch 80×80 mm2,
soft 8keV X-rays
Application
 XPCS (X-ray Photon Correlation
Spectroscopy)
Electrically testable using
 wire bonded connections
 bump-bonded connections
Tests in configuration with
 Sn-Pb bump-bonded sensor
 Fusion-bonded sensor
(Low-Temp. Direct bonding)
3D technology providers
 Tezzaron
 Ziptronix.
Collaborating institutions
Fermilab, AGH-UST, BNL
LTD-bonded vs b-bonded
Bump-bonded VIPIC1 pitch 100mm vs. 80mm for fusion-bonded, nevertheless …
competitive
to MAPS!
32×38 pixels bonded, 2880 pixels floating
bump-bonded: ENC=69.6 e- ± 5.1 mV/elarger input capacitance = larger noise,
lower gain and more dispersions
LARGE FEEDBACK RESISTANCE
ENC=36.2 e- ± 2.6 mV/esymmetrical noise distribution with
<3.4 % of pixels outside of ±3 s range
ENC on fusion bonded device is close to that measured for floating inputs!
ENC=40e- Cin<20fF, ENC=70e- Cin>80fF
16
From VIPIC1 to VIPIC-Large: 1Mpixel XCS Detector
X-ray back-side illumination
Features






1Mpixel = 3 shingles of 6×2 or straight 7×7 VIPICs-L LTD-bonded (D2W) to a sensor wafer
No dead edges, no peripheral circuitry on the ASIC
65 mm - pitch square pixel, 36,864 pixels/chip grouped in indiv. readout subchips of 1024 pixels
1 FPGA per VIPIC-L for on the fly data processing (up to 0.7 Tbps of raw data produced)
Multi-layer (>20 routing layer LTCC) supports b-bonded detector structure
Flat back-side - friendly for mounting of a cooling plate
17
B-TSV
TSVs are critical component for
VIPIC-Large
 small diameter ~1mm TSVs
 wire-bond-less
 no-dead-zone
Middle
TEOS SiN
1470A
469A
Via-Last TSVs (inserted in postprocessing after thinning of a 3D bonded
wafer pair)
 B-TSV (requirement: identical DRC as
GF TSVs)
Work with Tezzaron/Novati on B-TSVs
 Bosch etching used for B-TSV cavities
and internal metal (M1) is Cu
- DRC rules = GF TSV rules
- 2 3D-integrated wafer pairs tested
18
Bottom
Top
Oxide
SiN
B-TSVs – capacitance and resistance
B-TSV to substrate capacitance
B-TSV resistance
1TSV
2TSVs
TSVs to substrate breakdown
voltage measurement:
 W#5 VBREAK=38.5V ± 9V
 W#6 VBREAK=36.5V ± 5V
19
Single B-TSV resistance is a difference
between 1TSV/connection and
2TSV/connection  0.343W.
Wafer #6 showed more defective BTSV in the chains
VIPIC-L Design Highlights
New approach for entirely edgless design – enabled by 2 tier 3D integrations
 array of pixels on the analog tier
 whole digital tier P&R-ed at once without respecting pixel boundaries
32×32 VIPIC-L analog pixels forming single
analog tier subchip
(6×6 subchips form one full analog tier chip)
20
Digital tier chip designed in 130nm process;
next design is clearly 65nm or beyond
32×32 pixels VIPIC-L digital tier subchip
with no explicit boundaries of pixels
The PixFEL Project
 Long term goal: Develop a four-side buttable module for the assembly of large
area detectors with no or minimum dead area to be used at FEL experiments
 Collaboration: INFN (PV,PI,TN) UniPV, UniPi, UniBI, UniTN
Multilayer device: active edge thick pixel sensor, two tiers 65 nm CMOS readout
chip (analog+digital/memory) with low/high density TSV, pixel pitch of 100 mm
21
Demonstrator
slim edge sensor
high density
interconnects
bump
bonding
TSVs
front-end
& ADC
readout active/slim
chip
edge sensor
hybrid board
memory and
digital readout
Interconnection and vertical integration
bond
pads
Main features
 32x32 array of hybrid pixels
 three-tier structure
 slim edge, fully depleted silicon
sensor
 two-tier readout chip, in 65 nm
CMOS technology
 1 layer with analog front-end
and ADC
 1 layer devoted to digital
memory
• Sensing layer - front-end chip: relatively large pitch of 100um easily achieved
through bump-bonding techniques
• Through silicon vias (TSVs) to access the circuits from the back side and including
substrate thinning
• 3D integration to interconnect the analog front-end and ADC on one tier to the
memories on the other tier
22
Summary
 Pixel detector requirements for next
generation experiments at high luminosity
colliders and X-ray sources are extremely
challenging
•
•
•
•
high granularity → small room for electronic
high hit rate → high speed, on-chip memory
data reduction → hit discrimination capability
radiation hardness
 More functionalities need to be built into the
readout chip to satisfy the specifications
• front-end performance improvement
• data selection and hit discrimination
(bandwidth reduction)
3D integration technologies may provide several advantages in the design
of detectors for vertexing and imaging applications
23