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Module- 3
Bipolar Junction Transistor (BJT)
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Transistor Introduction:• Invented in 1948 by John Bardeen, Walter Brattain
and Willium Shockley at Bell Labs USA.
• They got Nobel Prize in 1956; first time given for
an engineering device rather than for a concept.
• These replaced bulky vacuum tubes.
• Later, field effect transistors (FETs), were
developed.
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 Transistor stands for the transfer of resistance.
 Three terminal, two junction, three layer device
 O/P voltage, power or current can be controlled by I/P
current so it is a current controlled device.
 Bipolar means flow of current due to the two types of
carrier i.e. electron and holes both.
 Three layers of Emitter, base and collector.
 Three terminals are emitter, base and collector.
 Two junction J1 is emitter-base junction & J2 is the
base-collector junction.
 The order of doping is Emitter>>Collector>Base.
 The order of width is Collector>>Emitter>Base.
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BJT :- BJT means Bipolar Junction Transistor.Transistor is passing the
signal from a region of low resistance to a region of high resistance.The
concept of transfer of resistance has given the name transistor
(Transfer-Resistor).
TRANSISTORS
Unipolar junction transistor
(The current conduction is due
to one type of carriers,i.e.
majority carriers.)
Eg. FET
 Voltage controlled device
 Small gain bandwidth product
 Large switching time
 Has no offset voltage
Bipolar junction transistor
(The current conduction is
due to both types of charge
carriers majority and
minority.) Eg. BJT
Current controlled device
Large gain bandwidth
product
Medium switching time
Has offset voltage
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BJT’s are basically of two types :N-P-N and P-N-P type.It is a three terminal device.
Collector
J1
J2
Base
N-P-N Transistor
Emitter
Collector
J1
Base
J2
Emitter
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Construction of BJTs:-
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In n-p-n current is due to majority charge carrier i.e. electron.
In p-n-p current is due to majority charge carrier i.e. holes.
Biased Transistor :- According to the voltage applied across two
junctions of transistors ,the transistor can work in four different regions.
S.No.
Region
Emitter-Base
jun. (J1)
Collector-Base Application
Jun. (J2)
1.
Active
Forward biased Reverse biased Amplifiers
2.
Cut-off
Reverse biased Reverse biased Switch
3.
Saturation
Forward biased Forward biased Switch
4.
Inverted
Reverse biased Forward biased Hardly used
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1. Active Region:Junction (E-B) J1 is forward biased & (B-C)J2 is reverse biased
The collector current depends upon the base current.
Emitter-Base
Junction J1
Collector-Base
Junction J2
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Working of A Transistor :-
Fig. 3.4(a) Working of Transistor
The Emitter current is the sum of the collector current & base current.
Mathematically,
IE=IC+IB
………….(1)eq.
The current due to thermally generated minority carrier which pass
towards the base. This small current is called reverse saturation current.
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The emitter current of a transistor consists of two components. These
are base current & collector current but the base current is only about
2% of the emitter current whereas the collector current is the 98% of
the emitter current.
So, eq.(1) can also be written as,
I E  IC
....eq.(2)
IB  0
....eq.(3)
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Transistor current equation:-
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2. Cut-off Region:Junction (E-B) J1 is reverse biased & (B-C) J2 is reverse biased.
The collector current becomes zero only few thermally generated
minority carriers are available.
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3. Saturation Region:Junction (E-B) J1 is forward biased & (B-C) J2 is forward biased.
The collector current becomes independent of the base current
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4. Inverted
Region:-
Junction (E-B) J1 is reverse biased & (B-C) J2 is forward biased.
Transistor action is poor.
The collector cannot inject the majority carrier
into the base.
NPN
C
VEB
B
+
-
E
VCB
+
Fig 3.3(d) Inverted Region of Transistor
Transistor rarely used in this mode.
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Basic Amplifier:
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TRANSISTOR CONFIGURATION:(..Depends upon the one terminal
Transistor Configuration
which is grounded)
Common Base
..The I/P is bet E-B &
O/P is bet B-C
Common Emitter
Common Collector
..The I/P is bet B-E &
O/P is bet E-C
..The I/P is bet B-C &
O/P is bet C-E
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TRANSISTOR CONFIGURATION
Common Base Configuration : When base is common both at input
and output side.
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Leakage Current in C-B Configuration:SW
NPN
E
C
- VEE
+
RC
+
B
VCC
Common Base Configuration
When SW is open then no emitter current so no base & collector
current. But C-B junction is reverse biased, minority carriers diffuse
across the C-B junction & this produces a small current. This small
current is called leakage current & is denoted by ICBO or ICO means
the leakage current bet. C-B with emitter open.
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Current Gain in Common Base Configuration:RE
- VEE
+
E
NPN
C
IE
RC
IC
IB
+
-
VCC
B
Common Base Configuration
 D.C. current gain in C-B mode may be defined as the ratio of (IC) collector
current to the emitter current (IE). It is denoted by α or αdc of hFB
α = αdc= hFB= IC/IE
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 A.C. current gain may be defined as the ratio of (ΔIC) change in
collector current to the change in emitter current (ΔIE) for a constant
collector to base voltage. It is denoted by αo or αac of hfb
αo = αac= hfb= ΔIC/ΔIE
 The value of α is always less than 1. but practically it is approx. 0.90
to 0.98.
for practical purpose we say,
αdc = αac
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C-B Characteristics:-
CB configuration of P-N-P Transistor
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C-B Input Characteristics:-
C-B Input Characteristics
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C-B Output Characteristics:-
C-B Input Characteristics
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C-B Transfer Characteristics : -
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Early effect : The increase in the emitter current in the input
characteristics of C-B transistor is due to “Early effect”.The width of the
base region occupied by charge particles is known as effective width of
the base region.Since doping in the base is substatially smaller than that
of the collector, the penetration of the transition region into the base is
much larger than into the collector.Hence base deplition region is
large.When reverse bias voltage VCB increases, the width of depletion
region in base region also increases, which reduces the effective base
width.Due to reduction of the effective base width, now there are more
charge particles per unit area.In other words, due to reduction of the
effective base width, concentration of the charge gradient increases in
the base region.This increase in concentration of charge particles
causes more diffusion of electrons from n-type emitter to p-type base
increasing emitter current slightly.
where, ε = 8.854x10-12 F/m
e = 1.609x10-19 C
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C-E Configuration : When emitter is common both at input and output
side.
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Leakage Current in C-E Configuration:IB=0
+
VBB
RB
RC
C
IC
B
IE
-
+
VCC
-
E
Common Emitter Configuration
When switch is open the E-B junction is open circuit & so
input base current is zero but a leakage current ICEO flows
between C-E.
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Current Gain in Common Emitter Configuration:IB
+
VBB
RB
RC
C
IC
B
IE
-
+
VCC
-
E
Common Emitter Configuration
 D.C. current gain in C-E mode may be defined as the ratio of (IC)
collector current to the Base current (IB). It is denoted by β or βdc of
hFE
β = βdc= hFE= IC/IB
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 A.C. current gain in C-E configuration may be defined as the ratio of
(ΔIC) change in collector current to the change in base current (ΔIB)
for a constant collector to emitter voltage VEB. It is denoted by βo or
βac of hfe.
βo = βac= hfe= ΔIC/ΔIB
 The typical value of β may be from 20 to 300.
for practical purpose we say,
βdc = βac
 βo or βac is also known as common emitter short circuit current gain.
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C-E Characteristics : -
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C-E Input Charateristics
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C-E Output Characteristics :
34
C-E Transfer Characteristics :
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C-C Configuration : When collector is common both at input and output
side.
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Current Gain in Common Collector Configuration:IB
+
VBB
-
RB
RE
E
IE
B
IC
+
VEE
-
C
Common Collector Configuration
In C-C configuration the ratio of change in emitter
current (ΔIE) to the change in Base current (ΔIB) is
called as current gain or current amplification
factor. It is denoted by γ (Gamma).
γ = ΔIE/ΔIB
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C-C Input Characteristics :
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C-C Output Charateriistics :
39
C-C Transfer Characteristics :
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Relation between α and β : Now dividing the above equation by IC we get
We know that
,
So putting the values of α and β, we get
or
and
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IE = IB+IC
ICEO (It is the current in the collector to emitter junction when base is
open).
Therefore total current is
IC(total)= IC(maj.)+ICEO(min.)
we know that
..……eq.(1)
we know from C-B transistor
….…..eq.(2)
Compairing eq. (1) and eq. (2) we get
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Relation between α, β and γ :
we know that
Divide the above eq. by IB we get
We know,
Therefore ,
and
or
[∵
]
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3.16 Comparison between Transistor Config:Sr.
No.
Parameter
CB Conf.
CE Conf.
CC Conf.
1.
I/P Impedance
2.
O/P Impedance
Current Gain
Low
(50KΩ)
High
(10KΩ)
High (100)
Very High
(750KΩ)
Low (50Ω)
3.
Very Low
(40Ω)
Very High
(1MΩ)
Less than 1
4.
Voltage gain
Small (150)
High (500)
Less than 1
5.
Leakage Current
6.
Application
5μA for Ge &
1μA for Si
As a Buffer
500μA-Ge
& 20μA-Si
As an
Amplifier
500μA -Ge
& 20μA -Si
Impedance
Matching
High (100)
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Fig. 1
45
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47
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Junction voltages for a typical n-p-n transistor at 25° C
Type
VCE(sat)
VBE(sat)
VBE(active)
VBE(cut in)
VBE(cut off)
Si
0.2
0.8
0.7
0.5
0.0
Ge
0.1
0.3
0.2
0.1
-0.1
Q1. If β= 100,ICBO=10µA and IB=80µA.Find IE.
Sol. IE=IB(1+β)+(1+β)ICBO
IE=(1+100)80µA+(1+100)10µA
IE = 9.09mA
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Q2. If α=0.98, ICBO=10µA and IB=100µA, find IE.
Sol.
=
IE=(1+β)IB+ICBO(1+β)
=(49+1)100µA+(1+49)10µA
= 5.5mA
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D.C. Load Line : In order to operate transistor in the desired region we
have to apply external dc voltages of correct polarity.This is known as
biasing.Since it is d.c voltages therefore it is known as d.c biasing of the
transistor.
When we bias a transistor we establish certain current and
voltage conditions for the transistor.These conditions are known as d.c
operating conditions or d.c operating point or quiescent point.It should
be stable.It has a effect of change in β, ICO, VBE.
The intersection of the dc bias value of IB with the dc load line
determines the Q-point,It is desirable to have the Q-point centred on the
load line.
Purpose of the D.C biasing circuit:
 To turn the device ‘ON’.
 To place it in operation in the region of its characteristics where the
device operates most linearly, i.e. to set up the initial d.c values of IB, IC,
and VCE.
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•
The O/P collector current IC & collector to emitter voltage VCE
conditions in the transistor ckt are represented by a point on the O/P
characteristic curve. The same information can be obtained by the
d.c. load line.
Basic CE amplifier
D.C. equivalent Ckt. of52CE
Amplifier
VCC/RC
Operating Point or Quiescent
Point.
B
Q
D.C. Load Line
VCC
A
Applying KVL to the collector portion of circuit, we have
ICRC + VCE = VCC
VCC
1
IC = VCE +
RC
RC
... eq.(1)
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The above equation is the form of
Y = mX + C
.. eq(2)
now compairing eq(1) with eq(2) we get,
1
The slope of the straight line is m = RC
To plot the d.c. load line we use that on VCE axis the
IC is zero and on IC axis the VCE is zero.
now putting these conditions in eq.(1) we get,
VCC = VCE + ICR C
when IC = 0 ⇒VCE = VCC
Point A ≡(VCC ,0)
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when VCE = 0 ⇒VCC = ICRC
VCC
VCC
or IC =
,Point B ≡ 0,
RC
RC
So the operating point or quiescent point can be given as,
VCC
Q ≡ VCC,
= (VCE ,IC )
RC
 The line AB is called load line because its slope depends upon the
value of resistor RC which is the load of the d.c. circuit.
 The zero signal values (no a.c. signal) of collector current IC &
collector to emitter voltage VCE are known as the operating point.
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Its significance is that regardless of the behaviour of the transistor, the
collector current IC and the collector-emitter voltage VCE must always lie
on the load line, depends only on the VCC, RC and RE.
A Q point is when no ac input signal is applied to the transistor and
therefore it has constant dc values of IC and VCE.Q means quiescent
(latent) meaning at rest.
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Operating point(Q-point) near saturation gives clipping at the positive peak
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Operating point(Q-point) near cut off gives clipping at the negative peak
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Operating point(Q-point) at the centre of the active region is most suitable
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