Transcript UNIT I _II

3-phase half-wave converter
In general, for an m-phase half-wave converter,
the mean output voltage is given by
If m = 3 (3-phase),
1.The mean output voltage is zero for
2.Negative average output voltage occurs when
3.Power inversion is possible , if a load with an e.m.f. to
assist the current flow.
• With an RL load, at
Vdc = 0, the load
current falls to zero. Thus, continuous load
current does not flow for an RL load for
α ≥∏/2.
Half-wave controlled rectifier with
free-wheeling diode
The diode prevents the load voltage from going negative, thus inversion is not possible
• For α ≥∏/6, voltage zeros occur
and the negative portions in the
waveforms do not occur. The
mean output voltage is given by
Vdc 
3 3
Vm cos 
2
0
• For α≤∏/6 , without
voltage zeros occurring, the
mean output voltage is
given by

6
Vm 
Vdc 
 sin t dt
2   
3 6


5
 
6
6
Vm

(1  cos(   ))
6
2
3
A delay angle of greater than would imply a negative
output voltage, clearly not possible with a freewheeling load diode.
3-phase full converter
For , the output voltage is non-zero at all instances, hence the load current is
continuous for any passive load. Beyond
, the load current may be discontinuous.
For
, the current is always discontinuous for passive loads. Power inversion is
possible with an e.m.f. source. If inversion is not required, a free-wheeling diode is
normally used
Overlap
• Overlap is the phenomenon due to the effect
of source inductance on the a.c. side. The
current commutation is delayed due to the
source inductance which is normally the
leakage reactance of a transformer (as X >> R
for a transformer, the source resistance is
usually neglected).
• The waveforms with commutation period,
denoted by  during which both the outgoing
diode and incoming diode are conducting.
• This period is also known as “overlap” period.
During the overlap period, the load current is the
addition of the two diode currents, the
assumption being made that the load is inductive
enough to give a constant load current.
• The load voltage is the mean of the two
conducting phases during overlap period. The
effect of overlap is to reduce the mean output
voltage.
A circulating current i can be considered to flow in the closed path formed by the 2
conducting diodes D1 and D2. Ignoring the diode voltage drop
di
di
dt
dt
The voltage V2 - V1 = the difference between the two phases
= 0 at time zero. (t = 0)
V2  V1  L
For t > 0, the voltage
Vm :
VL :
V2  V1 
3 Vm sin t

2 VL sin t
peak value of the phase voltage
r.m.s. line voltage
Therefore,
di
dt
3 Vm
i
 sin t dt
2L
3 Vm  cos t

C
2L

3 Vm sin t  2 L
L
At t = 0, i = 0
C
3 Vm
2L
Hence,
i
3 Vm
(1  cos t )
2L
Proof of v2 - v1,
v1  Vm sin(   1500 )
v2  Vm sin(   1500  2400 )
v2  v1   Vm {sin '  sin( '  2400 )}
  Vm {sin '  sin ' cos 2400  cos ' sin 2400 }
3
3
 Vm { sin ' 
cos ' }
2
2
 3

1
  3 Vm 
sin '  cos ' 
2
 2


3 Vm sin( '  1500 ) 
3 Vm sin 
v  v1  L
v
di
di
 v2  L
dt
dt
v1  v2
2
If the datum is shifted by 1500,
v1  Vm sin(   1500 )
v2  Vm sin(   1500  2400 )
v1  v2
1
 Vm {sin '  sin( '  2400 )}
2
2
1
 Vm {sin '  sin ' cos 2400  cos ' sin 2400 }
2
1
1
3
 Vm { sin ' 
cos ' }
2
2
2
1
 Vm cos( '  1500 )
2

 Vm sin
cos 
6
The overlap is complete when i = IL , at t  
3 Vm
(1  cos  ) ; X  L
2X
2 IL X
cos   1 
3 Vm
IL 
The mean output voltage is given by
5
6
Vdc

1


[  Vm sin  d   Vm sin
cos  d]
6

2
0
3 6 

3 3
Vm (1  cos  )
4
or
Vdc = Vdc without overlap - reduction of Vdc due to overlap.
(i)
Vdc without overlap =
1
2
5
6
 Vm sin t dt 
3

6
3 3 Vm
2
(ii) Reduction of Vdc due to overlap


v
1
2  0
3
2



 v1
3
di
dt 
dt
L
2
2 0
dt
3  IL
3L
3X

IL 
IL
 L di 
2 0
2
2
Vdc 
Since I L 
Vdc 
3 3
3X
Vm 
IL
2
2
3 Vm
(1  cos  )
2 X
3 3
Vm (1  cos  )
4
Overlap in controlled 3-phase
converter
It can be seen that with a firing delay angle , a finite voltage is present,
V2  V1  3 Vm sin( t  )
where t = time from the start of commutation, when i = 0.
 3 sin( t  )  2 L
di
dt
which gives
i
3 Vm
{cos   cos ( t  )}
2 L
Overlap being complete when i = IL and t = .
IL 
3 Vm
[cos   cos (   )]
2 L
Compared to the uncontrolled case  = 00, the overlap angle  is shorter and the current change during
commutation will be towards a linear variation. The mean voltage of the load is given by : 1 5  

 
Vdc 
[ 6 Vm sin  d   Vm sin cos  d]
2    
6
6
3
3 3

Vm [cos   cos (   )]
4
Remark :
1.
The location of the waveform during overlap is at a position midway between the
outgoing and incoming voltages .
2.
For the 2-phase waveform , the load voltage = 0 during overlap period.
Overlap for inversion
A d.c. machine as the load element, acting as a motor which the
converter rectifying . However, if the load voltage VL reverses and   900
the d.c. machine will act as a generator. If the machine runs in the same direction of rotation, it can
only generate by having its armature or field connections reversed
It is only possible to commutate current from thyristor T1 to
thyristor T2 while the instantaneous voltage of phase 2 is higher than
phase 1 (i.e. while V2 is less negative than V1). At  = 1800, V1 and V2
and the relative voltage between the two phase after this reverses , making
commutation impossible, hence
 1800
is the limit of operation.
When in the inverting mode, it is more usual to designate the firing
position as firing advance angle 
1800  .
The effect of the overlap period 
is to delay the commutation.
The waveform during overlap has a voltage midway between the incoming and outgoing voltage
The overlap angle  must be less than the firing advance angle .
In practice
can never be reduced to zero.