Transcript Peripherals & Enhanced FLASH

Peripherals & Enhanced FLASH
Enhanced FLASH
PIC16F87X and PIC16F62X
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
PIC16F87X Features at a Glance

8K x 14 FLASH Program
Memory
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
256 x 8 EEPROM Data
Memory
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USART
Min. 100K E/W
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25mA sink/source
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1 - 16-bit
2 - 8-bit
10-bit A/D
© 1999 Microchip Technology Incorporated. All Rights Reserved.

9-bit addressable

High Speed
Enhanced SPI
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All 4 SPI modes supported
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Microwire Support
Master I2C
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3 Timers
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Two Capture/Compare/PWMs
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368 x 8 Data Memory (RAM)
33 I/O ports
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Typ. 1000 E/W
Byte/Word Read/Write at VDD
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Hardware Write to I2C
devices
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In-Circuit-Serial Programming
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In-Circuit-Debugger
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Parallel Slave Port
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Peripherals & Enhanced FLASH
PIC16F62X Features at a Glance


18-pin package
Up to 2K x 14 FLASH
Program Memory
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Typ. 1000 E/W
Byte/Word Read/Write at
VDD
Min. 100K E/W
224 x 8 Data Memory (RAM)
16 I/O ports

25mA sink/source
© 1999 Microchip Technology Incorporated. All Rights Reserved.
3 Timers

1 - 16-bit
2 - 8-bit
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Capture/Compare/PWM
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USART
128 x 8 EEPROM Data
Memory
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9-bit addressable
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High Speed
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2 Comparators
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In-Circuit-Serial Programming

Internal RC Oscillator
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Peripherals & Enhanced FLASH
FLASH Program & Data EEPROM:
Programming/Erase Operation
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Program timing controlled by an internal RC
oscillator.
Timeout set for ~2mS per word.
When timeout occurs, EEIF flag is set.
Read operation has to be done to verify write.
Write operation sequence has to be followed for
each location:


Write 0x55 then 0xAA to EECON2, then set write flag.
Failure to follow sequence aborts write operation.

Advantage: Prevents inadvertent write operations.
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
FLASH Program
and Data EEPROM Memory
S. F. R.
EEADRH
8
13
FLASH Program
Memory
8K X 14
EEADR
8
256 X 8
Data
EEPROM
Memory
14
EEDATH EEDATA
EECON1
EECON2
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
FLASH Program Memory:
Three Programming Modes
 Low Voltage ICSP mode (Default mode):

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Programming at VDD (typically 5V).
RB3/PGM pin dedicated as Program Mode Select.
 High Voltage ICSP mode:
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High voltage (13V) required on MCLR/VPP pin.
Same ICSP mode as in many other PICmicro® MCUs.
RB3/PGM pin can be used as normal I/O.
 Internal Program Write mode:


Single word writes during program execution.
Example: Calibration constants etc.
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
FLASH Program Memory:
Low Voltage ICSP Mode (Default)
VDD
PIC16F87X or
PIC16F62X
PIC16F87X or PIC16F62X
Enters LV Programming Mode
RB3
VSS
RB6
CLK
RB7
DATA
VDD
VDD
MCLR
VDD
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
FLASH Program Memory:
High Voltage ICSP Mode
PIC16F87X or
PIC16F62X
RB6
CLK
RB7
DATA
5V
+5V
VDD
VDD
13V
MCLR
© 1999 Microchip Technology Incorporated. All Rights Reserved.
PIC16F87X or PIC16F62X enters
High Voltage ICSP™ Mode
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Peripherals & Enhanced FLASH
FLASH Program Memory:
Internal Program Write Mode
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During normal program execution, a device can
write to its own program space.
VDD can be at any operating level: 2.0V to 5.5 V.
Erase automatically precedes the write to the word.
Application Usage:
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Storing calibration constants for sensors and transducers in program
memory.
Field re-calibration of constants.
Remote re-programming of sections of code excluding code
protected areas.
Checksum.
Code revisions.
Tech Briefs: TB025 and TB026.
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
FLASH Program Memory:
Read/Write Operations Over Voltage

Internal Read/Write Operations:
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Can always read any locations at any voltage.
When writes are enabled, can write at any voltage.
External (ICSP) Read/Write Operations:

When enabled:
 Read from any location over voltage.
 Perform a write to a single location over voltage.
 Perform an erase/write cycle to a single location
over voltage.
 Bulk erase when VDD > 4.5V.
© 1999 Microchip Technology Incorporated. All Rights Reserved.
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Peripherals & Enhanced FLASH
Data EEPROM Memory:
Reading Locations
BSF
BCF
MOVLW
MOVWF
BSF
BCF
BSF
BCF
MOVF
STATUS,RP1
STATUS,RP0
ADDRESS
EEADR
STATUS,RP0
EECON1,EEPGD
EECON1,RD
STATUS,RP0
EEDATA,W
© 1999 Microchip Technology Incorporated. All Rights Reserved.
Program:
;Move to Bank2
;Write data memory address
into the EEADR register
;Move to Bank3
;Point to Data Memory
;Start the Read Operation,
data will be available in
the very next Tcy
;Move the data into W
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Peripherals & Enhanced FLASH
Data EEPROM Memory:
Writing to Locations
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
STATUS,RP1
STATUS,RP0
ADDRESS
EEADR
VALUE
EEDATA
STATUS,RP0
EECON1,WREN
EECON1,EEPGD
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
EECON1,WREN
© 1999 Microchip Technology Incorporated. All Rights Reserved.
;Move to Bank2
;Write desired address to EEADR
;Write desired data to EEDATA
;Move to Bank3
;Enable EEPROM writes
;Disable interrupts
;Point to data memory
;Next five instructions are required
;sequence to initiate a write sequence
;Initiate the write sequence
;Enable interrupts
;Disable EEPROM writes, does not affect
the current write cycle
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Peripherals & Enhanced FLASH
FLASH Program Memory:
Reading Locations
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
NOP
NOP
BCF
MOVF
MOVWF
MOVF
STATUS,RP1
STATUS,RP0
ADDRH
EEADRH
ADDRL
EEADR
STATUS,RP0
EECON1,EEPGD
EECON1,RD
STATUS,RP0
EEDATA,W
Temp
EEDATH,W
© 1999 Microchip Technology Incorporated. All Rights Reserved.
;Move to Bank2
;Write data memory address into
;the EEADRH:EEADR register
;Point to program memory
;Start the Read Operation, data will
;be available in the third TCY
;Move the data into W
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Peripherals & Enhanced FLASH
FLASH Program Memory:
Writing to Locations
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BSF
BCF
EEADDRH
ADDRH
EEADRH
ADDRL
EEADR
DATAH
EEDATH
DATAL
EEDATA
STATUS,RP0
EECON1,WREN
EECON1,EEPGD
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
EECON1,WREN
© 1999 Microchip Technology Incorporated. All Rights Reserved.
;Move to Bank2
;Write desired address to EEADRH:EEADR
;Write desired data to EEDATH:EEDATA
;Move to Bank3
;Enable EEPROM writes
;Point to program memory
;Disable interrupts
;Next five instructions are required
;sequence to initiate a write sequence
;Initiate the write sequence
;Instruction is executed normally
;Instruction is ignored, processor halts
;Enable interrupts
;Disable EEPROM writes
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