Transcript A Single-supply True Voltage Level Shifter

A Single-supply True
Voltage Level Shifter
Rajesh Garg
Gagandeep Mallarapu
Sunil P. Khatri
Department of Electrical and Computer Engineering,
Texas A&M University,
College Station, TX
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Outline
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Introduction
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Previous Work
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Our Approach
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Experimental Results
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Conclusions
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Introduction
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System-on-chip and multi-core computing architectures
Increasingly used for many applications
 Employ voltage scaling to meet power and energy
requirements
 Contain many voltage domains operating at different
supply voltage levels
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Different voltage domains communicate with each
other
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Efficient voltage level shifters (VLS) are required to
interface these voltage domains
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Should be fast, and also consume low power (leakage and
dynamic)
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Introduction
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Input (VDDI) and output (VDDO) domains
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When VDDI > VDDO, an inverter can be used
When VDDI < VDDO, special VLS required.
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DVS is employed to further reduce power consumption
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In case an inverter is used, leakage may be too high.
Conventional VLS need two supply voltages
Need to route VDDI supply voltage along with signal wire
Supply wires are typically very wide
May result in routing congestion and excessive area utilization
At different times, VDDI can be greater than or less than VDDO
Conventional VLS’s need supply voltages of all input signals from
different domains
Further increase area utilization and make routing more complex
We would like to address both the above issues. In other
words…
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Introduction
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Need single supply VLS’s
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Need “true” VLS’s
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Perform voltage level conversions using only VDDO supply
voltage
This will ease placement and as well as routing constraints
The same VLS should handle the cases when VDDI < VDDO
and VDDI > VDDO
Our VLS presented is this talk meets these
requirements
No prior approach exist which can perform both
low-to-high and high-to-low voltage level conversion
using a single supply voltage
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Previous Work
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Several previous approaches utilize dual supply voltage
[ Wang et al. 2001, Tan et al. 2002]
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Puri et al. 2003 proposed single supply VLS to convert low
level to high voltage level
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Focused on minimizing power and energy consumption
Utilize both VDDI and VDDO supply voltages
Limited range of operation due to the usage of diode-connected
NMOS device to generate lower supply voltage
Leakage currents are higher when VDDO greater than VDDI + VT
Khan et al. 2006 addressed the issue of voltage range
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Can perform only low to high voltage level conversion
Higher leakage currents
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Our Single Supply-True VLS
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Convert signal level from VDDI domain to VDDO domain
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Using only VDDO supply
Works for VDDI < VDDO as well as VDDI > VDDO
VDDI
in
VDDI
Domain
GND
VDDO
node1
GND
VDDO
node2
GND
VDDO
outb
GND
Vctrl
ctrl
VTM 2
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Our Single Supply-True VLS
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Maximum voltage
at ctrl node
When VDDI < VDDO
Vctrl  min( VDDI ,VDDO  VTM 8 )
 When VDDI > VDDO
Vctrl  min( VDDO ,VDDI  VTM 7 )
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This means that when
in = VDDI (and node2 =
VDDO), M1 never turns
on, for both VDDI >
VDDO and VDDI < VDDO
Low VT device
All devices were sized
to reduce leakage currents
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VDDI
Domain
To minimize leakage
current, use high VT
devices
Speed and leakage power tradeoff
All transistors except M4, M6 and M8 are nominal VT
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Experimental Results
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Implemented our SS-TVLS in PTM 90nm
Compared with a combination of Inverter and
VLS of Khan et al. (Combined VLS)
Inverter is used when VDDI > VDDO
 VLS of Khan et al. when VDDI < VDDO
 Requires control signal
to indicate whether
VDDI < VDDO or
VDDI > VDDO
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Experimental Results
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Low-to-high conversion VDDI = 0.8V and VDDO = 1.2V
Performance Parameter
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Our SS-TVLS
Combined VLS
Ratio
Delay Rise (ps)
22
122.6
5.6
Delay Fall (ps)
33.3
50.5
1.5
Power Rise (mW)
27.6
71.87
2.6
Power Fall (mW)
33.8
119.27
3.5
Leakage Current High (nA)
20.8
157.2
7.6
Leakage Current Low (nA)
3.6
71.1
19.8
High-to-Low conversion VDDI = 1.2V and VDDO = 0.8V
Performance Parameter
Our SS-TVLS
Combined VLS
Ratio
Delay Rise (ps)
34.9
46.5
1.3
Delay Fall (ps)
15.7
35.2
2.2
Power Rise (mW)
27.3
20.7
0.8
Power Fall (mW)
59.3
56.8
1.0
Leakage Current High (nA)
7.3
32.5
4.5
Leakage Current Low (nA)
3.9
36.3
9.3
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Experimental Results
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Performed Monte Carlo simulations for process
and temperature variations
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3s = 10% for W, L and VT and for T = 27o, 60o and 90o C
Our SS-TVLS performs correctly in all Monte Carlo simulations
VDDI = 0.8V and VDDO = 1.2V
Performance Parameter
T = 27oC
Our SS-TVLS
VDDI = 1.2V and VDDO = 0.8V
Combined VLS
Our SS-TVLS
Combined VLS
m
s
m
s
m
s
m
s
Delay Rise (ps)
22.08
1.1
129.4
27.4
35.1
2.4
52
3.9
Delay Fall (ps)
33.2
1.9
50.4
6
15.6
0.8
34.8
1.3
Power Rise (mW)
27.7
0.8
78.9
7.3
27.5
1.3
22.5
1.1
Power Fall (mW)
33.8
0.4
114.2
7.2
59.5
0.6
52.5
0.1
Leakage Current High (nA)
31.5
13.7
218.8
158.6
8.6
3
41.4
14.1
Leakage Current Low (nA)
3.8
3.8
102.9
75.41
3.6
1.3
32.3
9.0
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Similar results are obtained for T = 60o and 90o C as well
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Experimental Results
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Voltage translation range
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Varied VDDI and VDDO from 0.8V to 1.4V in steps of 5mV
Our SS-TVLS performed efficiently for all VDDI and VDDO
combinations
Rising Delay
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Falling Delay
Performed layout of our SS-TVLS
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Area is 4.47mm2 ( Width = 0.837mm and height = 5.355mm)
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Conclusions
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Our single supply-true voltage level shifter can interface
different voltage domains
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The delay of our SS-TVLS is much lower than
combined VLS
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5.5x (1.3x) lower for a rising output when VDDI< VDDO
(VDDI > VDDO)
1.5x (2.2x) lower for a falling output when VDDI< VDDO
(VDDI > VDDO)
The leakage currents are also substantially lower for our
SS-TVLS compared to the combined VLS
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Convert any voltage level to any other desired voltage level by
using only VDDO supply voltage
7.5x (4.4x) lower for a high output and 19.5x (9.3x) lower for
a low output when VDDI< VDDO (VDDI > VDDO)
Our SS-TVLS is also more robust to process and
temperature variations
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THANK YOU!
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