Transcript DVS

Dynamic Voltage
Scaling Using Both
Headers and Footers
Kyle Craig and Roy Matthews
ECE 632
Background
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Our research has addressed the power savings method
known as Dynamic Voltage Scaling (DVS) to a system
and attempt to apply the use of both headers and footers
in the process.
Low power design is a crucial area of VLSI research and
quadratic power savings can be achieved by voltage
reduction, using the following formula: Pdyn=aCVDD2f.
DVS allows us to take advantage of this power savings.
We have performed simulations using a DVS system of
headers and footers on a 32-bit Kogge-Stone Adder
using the 65nm TT PTM
Voltage Scaling
Normalized Power
1.20
1.00
0.80
0.60
0.40
0.20
Power
Delay
0.00
0.6 0.7 0.8 0.9
1
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Normalized Delay
Normalized Power and Delay
1.1 1.2
VDD
The relationship between power and delay is shown above. Tradeoffs must be
considered when implementing a DVS system.
Header and Footer Sizing for Delay
Power (mW)
0.8
1.16
1.15
1.14
1.13
1.12
1.11
1.1
1.09
1.08
0.6
0.4
0.2
Delay
Power
0
25
50
75
100
125
150
175
Normalized Delay
VDDH Header Power and Delay
200
Width
0.8
1.16
0.6
1.14
0.4
Delay
Power
1.12
1.1
0.2
0
1.08
15
30
45
60
Width
75
90
115
Normalized Delay
Power (mW)
Footer Powe r and De lay
•Adding power gates to a system will
cause an increase in delay.
•Headers and footers must be sized
appropriately to achieve an
established metric.
•We can see using VDDH that a 50%
decrease in header width, a 1.1%
delay increase and 40% power
reduction.
•Similarly, using VSSL a 50%
decrease in footer width yields a
1.5% increase in delay and 13%
reduction in power.
Header and Footer Sizing for Delay
0.4
0.2
Delay
Power
25
50
75
100
125
150
175
1.16
1.15
1.14
1.13
1.12
1.11
1.1
1.09
1.08
Normalized Delay
•As before, if we use VDDL and
reduce width by 50%, the delay
increases by 2.1% and the power
decreases by 42%.
0.6
0
1.44
1.42
1.4
1.38
1.36
1.34
1.32
1.3
1.28
200
Width
VDDL Header Power and Delay
0.2
Power (mW)
•Comparing header sizing for VDDH
against VDDL shows that larger
headers are required to achieve a
similar delay metric.
Power (mW)
0.8
Normalized Delay
VDDH Header Power and Delay
0.15
0.1
0.05
Delay
Power
0
25
50
75
100 125 150 175 200
Width
Virtual Rail Recovery
Header Normalized Delay
Width/Delta T
50 (48.9)
90 (88.9)
Header Total Power (mW)
130 (129)
Width/Delta T
50 (48.9)
90 (88.9)
130 (129)
150
1.174
1.159
1.146
150
1.99
1.88
1.78
200
1.135
1.122
1.112
200
2.27
2.12
1.98
250
1.109
1.098
1.090
250
2.46
2.27
2.10
300
1.091
1.081
1.074
300
2.59
2.37
2.18
350
1.077
1.069
1.064
350
2.67
2.43
2.22
•The normalized delay can be seen here against total power for the system.
•Any time and width combination meeting our delay constraint of 10% is
highlighted.
•A global case without headers showed a power of 2.71mW, so every case
here saves some energy.
•Average total power is calculated here as the sum of the rail recovery power
and the power for the operation.
Virtual Rail Recovery
•Footer rail recovery can be seen here as compared to header rail recovery.
•Footers require a much smaller area to achieve the same delay penalty, which
can be leveraged when designing DVS circuits, though power savings is less
than for the header cases.
Header Normalized Delay
Width/Delta T
50 (48.9)
90 (88.9)
Footer Normalized Delay
130 (129)
Width/Delta T
50 (48.9)
90 (88.9)
130 (129)
150
1.174
1.159
1.146
75
1.103
1.095
1.090
200
1.135
1.122
1.112
100
1.081
1.075
1.071
250
1.109
1.098
1.090
125
1.067
1.062
1.060
300
1.091
1.081
1.074
150
1.057
1.054
1.052
350
1.077
1.069
1.064
175
1.049
1.047
1.046
Switching Energy Overhead
•Switching energy overhead is very
large in this case of an idle KoggeStone adder.
•This must be taken into account
when switching from VDDL to VDDH.
Width
Delay (ps)
Power(mW)
350
312.51
4.87
400
277.31
5.49
450
250.44
6.08
500
229.47
6.64
Sizing as a Knob
Power vs. Width
0.8
•These different slopes can
be leveraged as separate
knobs to achieve greater
control over power and
width.
0.6
Footer
0.5
0.4
0.3
0.2
Header
0.1
0
0
50
100
150
Normalized Width
200
250
200
250
Normalized Delay vs. Width
1.16
Normalized Delay
•Comparing the power
consumption of a system
only using headers versus
only using footers shows
some interesting results.
Power (mW)
0.7
Footer
1.15
1.14
1.13
Header
1.12
1.11
1.1
0
50
100
150
Normalized Width
Future Research
Circuit Body Bias
 Sensitivity Study of DVS with Headers and
Footers
 Tradeoffs for using both headers and
footers for leakage control (similar to
MTCMOS).

Conclusions
Any DVS system trades area for power
savings and designing for headers and
footers created additional complexity.
 However, such a system would allow for
more knobs, to give designers more
options when weighing power, delay, and
area considerations.
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