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DYNAMIC SYNCHRONIZER FLIP-FLOP PERFORMANCE IN FINFET TECHNOLOGIES NOCS 2014 Mark Buckler1, Arpan Vaidya2, Xiaobin Liu2, Wayne Burleson2,3 Cornell University1, University of Mass. Amherst2, AMD Research3 September 18, 2014 WHY ARE WE LOOKING AT SYNCHRONIZERS? Low power NoCs utilize fine grain DVFS Leads to Inter ClockDomain Communication • Requires synchronizers! • Error rates similar to that of transient faults Core 0 Core 1 Core 2 Cache Router Cache Router Cache Router Core 3 Core 4 Core 5 Cache Router Cache Router Cache Router Core 6 Core 7 Core 8 Cache Router Cache Router Cache Router Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 2 of 35 PROBLEM: METASTABILITY Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 3 of 35 THE BRUTE-FORCE SYNCHRONIZER Synchronizer reliability is quantified as the Mean Time Between Failures (MTBF) Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 4 of 35 SYNCHRONIZER FLIP-FLOP EVALUATION τ is the strongest circuit level term in calculating MTBF Goal 1: Provide NoC designers with τ simulations over design parameters Goal 2: Find the best Flip-Flops, and ensure that they can be used by NoC designers Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 5 of 35 SYNCHRONIZER FLIP-FLOP EVALUATION Flip-Flops: • PowerPC Flip-Flop • Dynamic Latch Flip-Flop • Psuedo-NMOS Flip-Flop Technology Nodes • Planar (50nm and 22nm) • FinFET (20nm, 10nm and 7nm) Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 6 of 35 SIMULATION TECHNIQUE Zhou and Ashouei et al, Microelectronics Journal, 2011 Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 7 of 35 EFFECT OF TECHNOLOGY CHANGE DLFF Power PC PseudoNMOS Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 8 of 35 VOLTAGE AND TEMPERATURE SENSITIVITY PseudoNMOS in 22nm DLFF in 22nm Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 9 of 35 VOLTAGE AND TEMPERATURE SENSITIVITY PseudoNMOS in 20nm DLFF in 20nm FinFETs are more sensitive to changes in threshold voltage from lower temperatures Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 10 of 35 EFFECT OF FORWARD-BODY BIASING 22nm (Planar) 20nm (FinFET) DLFF is best for high voltage, but we may have a problem... Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 11 of 35 THE DYNAMIC LATCH FLIP-FLOP A reset signal is necessary… Dike and Burton, IEEE SSC 1999 Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 12 of 35 THE DYNAMIC SYNCHRONIZER Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 13 of 35 THE DYNAMIC SYNCHRONIZER Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 14 of 35 THE DYNAMIC SYNCHRONIZER Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 15 of 35 BENEFITS OF THE DYNAMIC SYNCHRONIZER The Dynamic Synchronizer allows DLFFs to be used in typical synchronous systems Improves the latency-reliability tradeoff! • MTBF of 5,000 yrs over 5 yrs (same # of stages) or • Latency of 2 cycles over 3 cycles (same MTBF) Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 16 of 35 CONCLUSIONS Evaluated synchronizer τ values • τ continues to track with FO4 in FinFET • FinFET increases sensitivity to temperature • Body biasing still works for high voltage The Dynamic Synchronizer • We improved the latency-reliability tradeoff by enabling the use of low τ flip-flops Motivation • Flip-Flop Evaluation • The Dynamic Synchronizer • Conclusions Page 17 of 35