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Dr.Y.Narasimha Murthy Ph.D
[email protected]
• None other than Steve Sanghi, the chairman,
president and CEO of Microchip Technology
• Sanghi moved from India to U.S. to pursue a
Master’s degree at the University of
Massachusetts after bachelor’s degree in
engineering, from Punjab Engineering College.
• In 1993, Sanghi became president and CEO of
Microchip after seeking advice from venture
capital firms on starting his own company.
Since then, he has transformed Microchip
into a billion-dollar company specializing in
Microcontroller and analog semiconductors
used in devices ranging from remote
controls to cars. He also has been involved
in science and technology education
programs, and he’s been known to frequent
science fairs and question kids about their
Brief Introduction….
• The term PIC stands for “Peripheral
Interface Controller” .It is the brain child of
Microchip Technology, USA .They have
coined this name to identify their single
chip micro-controllers. These 8-bit micro
controllers have become very important
now -a -days in industrial automation and
embedded applications etc…..
• PICs are popular with both industrial
developers and hobbyists alike due to their
low cost, wide availability, large user base,
extensive collection of application notes,
availability of low cost or free development
tools, and serial programming (and reprogramming
• Microchip PIC
available in various types. When PIC
microcontroller MCU was first available
from General Instruments in early 1980's,
micro-controller had
a simple
instructions with basic I/O functions. These
architectures. They have limited program
memory and are meant for applications
requiring simple interface functions and
small program & data memories.
• Some of the low-end device numbers are
• 12C5XX
• 16C5X
• 16C505
• Mid range PIC architectures are built by
upgrading low-end architectures with more
number of peripherals, more number of registers
and more data/program memory.
• Some of the mid-range devices are
• 16C6X
• 16C7X
• 16F87X
Program memory type is indicated by an alphabet.
• F = Flash
• RC = Mask ROM
• One of the mid -range versions of PIC Cs
is PIC16C6x/7x. The 7x family has an
enhancement of Analog to Digital
converter capability. These Cs are
available with a range of capabilities
packaged in both dual in-line (DIP)
packages and surface-mount packages.
These are available in 28 pin DIP,40 pin
DIP ,44 pin surface mount package etc..
• In this 6x/7x family of Micro controllers ,
PIC 16C62A/PIC 16C74A are found with a
suffix A. some of PIC do not contain this A.
The presence of A indicates the brown-out
reset feature, which causes a reset of the
PIC when the Power Supply voltage drops
below 4.0 V.
Salient features
Speed :
When operated at its maximum clock rate
a PIC executes most of its instructions in
0.2 s or five instructions per
Instruction set Simplicity :
The instruction set is so simple that it
consists of just 35 instructions
Integration of operational features:
protection ensure that the chip operates
only when the supply voltage is within
specifications. A watch dog timer resets
the PIC if the chip malfunctions or
deviates from its normal operation at any
Programmable timer options:
Three timers can characterize inputs,
control outputs and provide internal
timing for the program execution.
Powerful output pin control:
A single instruction can select and drive
a single output pin high or low in its 0.2
s instruction execution time. The PIN
can drive a load of up to 25A.
I/O port expansion:
With the help of built in serial peripheral
interface the number of I/O ports can be
expanded. EPROM/DIP/ROM options
are provided.
I/O port expansion:
This is the most important aspect in the
PIC controllers.With the help of built in
Serial Peripheral Interface(SPI) the
number of I/O ports can be expanded.
EPROM/DIP/ROM options are provided.
Interrupt control:
Up to 12 independent interrupt sources
can control when the CPU will deal with
each sources.
• The PIC16CXX/17CXX is a family of low-cost,
high-performance, CMOS, fully-static, 8-bit
• There are Three Timers : Namely Timer 0,
Timer1, Timer 2
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler can
be incremented during sleep via external
• Timer2: 8-bit timer/counter with 8-bit period
register, pre- scaler and post- scaler
• Capture/Compare/PWM (CCP) module(s)
• Capture is 16-bit, max resolution is 12.5
ns, Compare is 16-bit, max resolution is
200ns, PWM max resolution is 10-bit
• Synchronous Serial Port (SSP) with SPITM
and I2C
• Universal Synchronous Asynchronous
Receiver Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
• Brown-out detection circuitry for Brown-out
Reset (BOR)
• PIC16CXX microcontroller family has
enhanced core features, eight-level deep
stack, and multiple internal and external
interrupt sources.
• The high performance of the PIC16CXX family
can be attributed to a number of architectural
microprocessors. To begin with, the PIC 16CXX
uses a Harvard architecture, in which, program
and data are accessed from separate memories
using separate buses. This improves bandwidth
over traditional Von Neumann architecture
where program and data may be fetched from
the same memory using the same bus.
• As the PIC 16c6x/7x family of micro-controllers
uses Harvard Architecture it
enables the
devices exceptionally fast execution speed for a
given clock rate. In the Harvard Architecture
separate buses are used for Data and
Instruction as shown in the diagram.
• Instructions are fetched from program memory
using buses that are distinct from the buses
used for accessing variables in data memory,
I/O ports etc. Every instruction is coded as a
single 14-bit word and fetched over a 14-bit wide
• Separating program and data buses
further allows instructions to be sized
differently than 8-bit wide data words.
Instruction op-codes are 14-bits wide
making it possible to have all single word
instructions. A 14-bit wide program
memory access bus fetches a 14-bit
instruction in a single cycle
• The PIC 16C61 addresses 1K x 14 of
program memory.
• The PIC16C62/62A/R62/64 addresses 2K
x 14 of program memory, and
• the PIC16C63/R63/65/65/65A/R65
devices address 4K x 14 of program
• The PIC 16C66/67 address 8K x 14
program memory. All program memory is
• The PIC16CXX can directly or indirectly address
its register files or data memory. All special
function registers including the program counter
are mapped in the data memory. The PIC16CXX
has an orthogonal (symmetrical) instruction set
that makes it possible to carry out any operation
on any register using any addressing mode. This
symmetrical nature and lack of “special optimal
situations” makes programming with the
PIC16CXX simple yet efficient, thus significantly
reducing the learning curve.
The CPU registers are
• Working Register (W)
• Status – Register
• FSR – File Select Register
• Program Counter
• Eight Level Stack
Working Register:
Working Register is used by many instructions
as the source of an operand. It also serves as
the destination for the result of instruction
execution and it is similar to accumulator in
other cs and ps. It is a 8-bit regarding.
Status Register:
It contains the arithmetic status of the ALU, the
RESET status and the bank select bits for the
data memory.
C: Carry/borrow bit
DC: Digit carry/borrow bit
Z: Zero bit
NOT_PD: Reset Status bit (Power-down
mode bit)
NOT_TO: Reset Status bit (tme- out bit)
RPO: Register bank Select
The bits 7 and 6 of Status Register are unused by
The ‘C’ bit is set when two 8-bit operands
are added together and a 9-bit result
occurs. This 9-bit is placed in the carry bit.
• The DC or Digit carry bit indicates that a
carry from the lower 4 bits occurred during
an 8-bit addition.
• Example: 0011 1000
0011 1000
0111 0000
Here DC=1 as a result of the carry from
the bit 3 to the bit 4 position.
• The Z or zero bits is affected by the execution of
arithmetic or logic instructions.
• The reset status bits NOT_TO and NOT_PD are
used in conjunction with PIC’s sleep mode. The
micro controller can put itself to sleep mode to
save power during intervals when it has nothing
to do. It can be reset by any of three kinds. Upon
reset the CPU can check these two reset status
bits to determine which kind of event resettled it
and then respond accordingly.
• The Register bank select bit RPO is used
to select either bank .
When RPO=0, select Bank 0, RPO=1,
select Bank 1.
• Example:
Select bank 0
Select bank 1.
FSR – (File Select Register):
It is the pointer used for indirect addressing. In
the indirect addressing mode the 8-bit register
file address is first written into FSR. It is a
special purpose register that serves as an
address pointer to any address through out the
entire register file.
INDF – (Indirect File):
It is not a physical register addressing this
INDF will cause indirect addressing. Any
instruction using the INDF register actually
access the register pointed to by the FSR.
PCL is actually the lower 8-bits of the 13-bit
program counter. It can be read like any other
PCLATH (Program Counter Latch):
The upper 3-bits of PCLATH remains zero and
serves no purpose, it is only when PC2 is
written to that PCLATH is automatically written
into the PC at the same time.
Memory organisation :
It has three memory blocks.
• Program memory
• Data memory
• Stack
Program Memory
The 6x/7x family controllers have either 2k or 4k
address of program memory. Normally a
program memory of 2k addresses needs only a
11-bit program counter to access any address
A program memory of 4k address needs a 12bit program counter. But this PIC family uses
13-bit program counter allowing the controllers
to an 8k-program memory without changing the
CPU structure.
• Two addresses in the program memory
address space are treated in a special way
by the CPU. The first address H’ 000’ being
a go to mainline instruction the second
special address, H’ 004’ being a ‘go to in
service’ instruction can be assigned to this
address to make the CPU to jump to the
beginning of the Interrupt Service routine
located elsewhere in the memory space.
• When we deal with tables, if any tables are
created they are assigned to addresses in
the range H’005 – H’0FF’. For most of the
applications this space is sufficient.
The main line program begins after the
Data memory (Register Files):
Data Memory is also known as Register
File. Register File consists of two
• General purpose register file ( RAM).
• Special purpose register file (similar to
SFR in 8051).
• The special purpose register file consists
of input/output ports and control registers.
Addressing from 00H to FFH requires 8
bits of address. However, the instructions
that use direct addressing modes in PIC to
address these register files use 7 bits of
instruction only. Therefore the register
bank select (RP0) bit in the STATUS
register is used to select one of the
register bank
Data Memory map
Block diagram
The PIC architectures have several limitations:
Only a single accumulator
A small instruction set
Operations and registers are not orthogonal;
some instructions can address RAM and/or
immediate constants, while others can only use
the accumulator
Memory must be directly referenced in arithmetic
and logic operations, although indirect
addressing is available via 2 additional registers
Register-bank switching is required to access
the entire RAM of many devices
Wish you good luck